# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.

[options]
# wordswap swaps labels if the pin is on the right side an looks like this:
#   "PB1 (CLK)". That's useful for micro controller port labels
# rotate_labels rotates the pintext of top and bottom pins
#   this is useful for large symbols like FPGAs with more than 100 pins
# sort_labels will sort the pins by it's labels
#   useful for address ports, busses, ...
wordswap=yes
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=1400
pinwidthvertical=300
pinwidthhorizontal=300

[geda_attr]
# name will be printed in the top of the symbol
# name is only some graphical text, not an attribute
# version specifies a gschem version.
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20090324 1
name=MCP3201
device=MCP3201
refdes=J?
footprint=DIL 8
description=MCP3201 2.7V 12-Bit A/D Converter with SPI(TM) Serial Interface
documentation=http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf
author=Wojciech Zabolotny <wzab@ise.pw.edu.pl>
dist-license=public domain
use-license=public domain
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=
#comment=

[pins]
# tabseparated list of pin descriptions
# ----------------------------------------
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets.
# net specifies the name of the net. Vcc or GND for example.
# label represents the pinlabel.
#	negation lines can be added with "\_" example: \_enable\_ 
#	if you want to write a "\" use "\\" as escape sequence
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	
#-----------------------------------------------------
1	1	pas	line	l		VREF
5	5	pwr	line	r		VDD
2	2	pas	line	l		IN+
6	6	in	line	r		CLK
3	3	pas	line	l		IN-
7	7	tri	line	r		DOUT
4	4	pwr	line	l		VSS
8	8	in	line	r		\_CS\_/SHDN

