# This is the template file for creating symbols with tragesym # every line starting with '#' is a comment line. # save it as text file with tab separated cells and start tragesym [options] # wordswap swaps labels if the pin is on the right side an looks like this: # "PB1 (CLK)". That's useful for micro controller port labels # rotate_labels rotates the pintext of top and bottom pins # this is useful for large symbols like FPGAs with more than 100 pins # sort_labels will sort the pins by it's labels # useful for address ports, busses, ... wordswap bracket rotate_labels yes sort_labels no generate_pinseq yes sym_width 4000 pinwidthvertical 300 pinwidthhorizontal 300 [geda_attr] # name will be printed in the top of the symbol # if you have a device with slots, you'll have to use slot= and slotdef= # use comment= if there are special information you want to add version 20100804 1 name ATmega32U2 device ATmega32U2 refdes U? footprint TQFP32_7 comment available footprints are: TQFP32_7, QFN32_7_EP description ATmega32U2/ATmega16U2/ATmega8U2 documentation http://atmel.com/dyn/resources/prod_documents/doc7799.pdf author Martin Kunz numslots 0 dist-license unlimited use-license unlimited #slot 1 #slotdef 1: #slotdef 2: #slotdef 3: #slotdef 4: #comment #comment #comment [pins] # tabseparated list of pin descriptions # # pinnr is the physical number of the pin # seq is the pinseq= attribute, leave it blank if it doesn't matter # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) # style can be (line,dot,clk,dotclk,none). none if only want to add a net # posit. can be (l,r,t,b) or empty for nets # net specifies the name of the net. Vcc or GND for example. # label represents the pinlabel. # negation lines can be added with "\_" example: \_enable\_ # if you want to write a "\" use "\\" as escape sequence # #pinnr seq type style posit. net label 1 io line l XTAL1 2 io line l PC0 (XTAL2) 24 io line l PC1 (\_Reset\_, dW) 5 io line l PC2 (PCINT11, AIN2) 26 io line l PC4 (PCINT10) 25 io line l PC5 (PCINT9, OC1B) 23 io line l PC6 (PCINT8, OC1A) 22 io line l PC7 (INT4, ICP1, CLKO) spacer l 27 pwr line l UCAP 28 pwr line l UGND 30 io line l D- 29 io line l D+ 31 pwr line l UVCC 4 pwr line l Vcc VCC 32 pwr line l AVCC 3 pwr line l GND GND 6 io line r PD0 (OC0B, INT0) 7 io line r PD1 (AIN0, INT1) 8 io line r PD2 (RXD1, AIN1, INT2) 9 io line r PD3 (TXD1, INT3) 10 io line r PD4 (AIN3, INT5) 11 io line r PD5 (XCK, AIN4, PCINT12) 12 io line r PD6 (\_RTS\_, AIN5, INT6) 13 io line r PD7 (\_HWB\_, T0, \_CTS\_, AIN6, INT7) spacer r 14 io line r PB0 (\_SS\_, PCINT0) 15 io line r PB1 (SCLK, PCINT1) 16 io line r PB2 (PDI, MOSI, PCINT2) 17 io line r PB3 (PDO, MISO, PCINT3) 18 io line r PB4 (T1, PCINT4) 19 io line r PB5 (PCINT5) 20 io line r PB6 (PCINT6) 21 io line r PB7 (OC0A, OC1C, PCINT7)