v 20081231 1
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{
T 200 3350 5 8 1 1 0 6 1
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T 350 3300 9 8 1 1 0 0 1
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T 350 3300 5 8 0 1 0 2 1
pintype=in
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P 0 3000 300 3000 1 0 0
{
T 200 3050 5 8 1 1 0 6 1
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T 200 2950 5 8 0 1 0 8 1
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T 350 3000 9 8 1 1 0 0 1
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T 350 3000 5 8 0 1 0 2 1
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P 0 2700 300 2700 1 0 0
{
T 200 2750 5 8 1 1 0 6 1
pinnumber=4
T 200 2650 5 8 0 1 0 8 1
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T 350 2700 9 8 1 1 0 0 1
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T 350 2700 5 8 0 1 0 2 1
pintype=in
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P 0 2400 300 2400 1 0 0
{
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pinnumber=5
T 200 2350 5 8 0 1 0 8 1
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T 350 2400 9 8 1 1 0 0 1
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T 350 2400 5 8 0 1 0 2 1
pintype=in
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P 0 2100 300 2100 1 0 0
{
T 200 2150 5 8 1 1 0 6 1
pinnumber=6
T 200 2050 5 8 0 1 0 8 1
pinseq=6
T 350 2100 9 8 1 1 0 0 1
pinlabel=VCCA
T 350 2100 5 8 0 1 0 2 1
pintype=pwr
}
P 0 1800 300 1800 1 0 0
{
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pinnumber=7
T 200 1750 5 8 0 1 0 8 1
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T 350 1800 9 8 1 1 0 0 1
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T 350 1800 5 8 0 1 0 2 1
pintype=pwr
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P 0 1500 300 1500 1 0 0
{
T 200 1550 5 8 1 1 0 6 1
pinnumber=8
T 200 1450 5 8 0 1 0 8 1
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T 350 1500 9 8 1 1 0 0 1
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T 350 1500 5 8 0 1 0 2 1
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{
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T 200 1150 5 8 0 1 0 8 1
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T 350 1200 5 8 0 1 0 2 1
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{
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T 350 900 5 8 0 1 0 2 1
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{
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P 0 300 300 300 1 0 0
{
T 200 350 5 8 1 1 0 6 1
pinnumber=12
T 200 250 5 8 0 1 0 8 1
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T 350 300 9 8 1 1 0 0 1
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T 350 300 5 8 0 1 0 2 1
pintype=in
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{
T 2200 3650 5 8 1 1 0 0 1
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T 2200 3550 5 8 0 1 0 2 1
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T 2050 3600 9 8 1 1 0 6 1
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T 2050 3600 5 8 0 1 0 8 1
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{
T 2200 3350 5 8 1 1 0 0 1
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T 2200 3250 5 8 0 1 0 2 1
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T 2050 3300 9 8 1 1 0 6 1
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T 2050 3300 5 8 0 1 0 8 1
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P 2400 3000 2100 3000 1 0 0
{
T 2200 3050 5 8 1 1 0 0 1
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T 2200 2950 5 8 0 1 0 2 1
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T 2050 3000 9 8 1 1 0 6 1
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T 2050 3000 5 8 0 1 0 8 1
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P 2400 2700 2100 2700 1 0 0
{
T 2200 2750 5 8 1 1 0 0 1
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T 2200 2650 5 8 0 1 0 2 1
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T 2050 2700 9 8 1 1 0 6 1
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T 2050 2700 5 8 0 1 0 8 1
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P 2400 2400 2100 2400 1 0 0
{
T 2200 2450 5 8 1 1 0 0 1
pinnumber=20
T 2200 2350 5 8 0 1 0 2 1
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T 2050 2400 5 8 0 1 0 8 1
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P 2400 2100 2100 2100 1 0 0
{
T 2200 2150 5 8 1 1 0 0 1
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T 2050 2100 9 8 1 1 0 6 1
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{
T 2200 1850 5 8 1 1 0 0 1
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T 2200 1750 5 8 0 1 0 2 1
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T 2050 1800 9 8 1 1 0 6 1
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T 2050 1800 5 8 0 1 0 8 1
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P 2400 1500 2100 1500 1 0 0
{
T 2200 1550 5 8 1 1 0 0 1
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T 2200 1450 5 8 0 1 0 2 1
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T 2050 1500 9 8 1 1 0 6 1
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T 2050 1500 5 8 0 1 0 8 1
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P 2400 1200 2100 1200 1 0 0
{
T 2200 1250 5 8 1 1 0 0 1
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T 2200 1150 5 8 0 1 0 2 1
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T 2050 1200 9 8 1 1 0 6 1
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T 2050 1200 5 8 0 1 0 8 1
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P 2400 900 2100 900 1 0 0
{
T 2200 950 5 8 1 1 0 0 1
pinnumber=15
T 2200 850 5 8 0 1 0 2 1
pinseq=22
T 2050 900 9 8 1 1 0 6 1
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T 2050 900 5 8 0 1 0 8 1
pintype=pwr
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P 2400 600 2100 600 1 0 0
{
T 2200 650 5 8 1 1 0 0 1
pinnumber=14
T 2200 550 5 8 0 1 0 2 1
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T 2050 600 9 8 1 1 0 6 1
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T 2050 600 5 8 0 1 0 8 1
pintype=out
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P 2400 300 2100 300 1 0 0
{
T 2200 350 5 8 1 1 0 0 1
pinnumber=13
T 2200 250 5 8 0 1 0 2 1
pinseq=24
T 2050 300 9 8 1 1 0 6 1
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T 2050 300 5 8 0 1 0 8 1
pintype=pas
}
B 300 0 1800 3900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 2100 4000 8 10 1 1 0 6 1
refdes=U?
T 300 4200 5 10 0 0 0 0 1
device=SN65LVDS352
T 300 4400 5 10 0 0 0 0 1
footprint=TSSOP24
T 300 4600 5 10 0 0 0 0 1
author=Stefan Salewski
T 300 4800 5 10 0 0 0 0 1
documentation=http://www.ti.com/lit/gpn/sn65lvds352
T 300 5000 5 10 0 0 0 0 1
description=Quad High-Speed Differential Receivers
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numslots=0
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dist-license=GPL
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use-license=unlimited
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comment=generated with Python script tragesym
T 300 4000 5 10 1 1 0 0 1
value=SN65LVDS352