v 20091004 2
T 0 5300 8 10 0 0 0 0 1
device=connector
T 0 5100 8 10 0 0 0 0 1
footprint=spi_vs1011
B 0 2800 1100 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1000 3000 1300 3000 1 0 1
{
T 900 3100 5 6 1 1 0 0 1
pinnumber=4
T 2800 3000 5 8 0 0 0 0 1
pinseq=4
T 800 3000 9 10 1 1 0 6 1
pinlabel=SCK
T 3600 3000 5 8 0 0 0 0 1
pintype=io
T 4400 3000 5 10 0 0 0 0 1
netname=SCK
}
P 1000 3800 1300 3800 1 0 1
{
T 900 3900 5 6 1 1 0 0 1
pinnumber=2
T 2800 3800 5 8 0 0 0 0 1
pinseq=2
T 800 3800 9 10 1 1 0 6 1
pinlabel=MISO
T 3600 3800 5 8 0 0 0 0 1
pintype=io
T 4400 3800 5 10 0 0 0 0 1
netname=MISO
}
P 1000 3400 1300 3400 1 0 1
{
T 900 3500 5 6 1 1 0 0 1
pinnumber=3
T 2800 3400 5 8 0 0 0 0 1
pinseq=3
T 800 3400 9 10 1 1 0 6 1
pinlabel=MOSI
T 3600 3400 5 8 0 0 0 0 1
pintype=io
T 4400 3400 5 10 0 0 0 0 1
netname=MOSI
}
P 1000 4200 1300 4200 1 0 1
{
T 900 4300 5 6 1 1 0 0 1
pinnumber=1
T 2800 4200 5 8 0 0 0 0 1
pinseq=1
T 800 4200 9 10 1 1 0 6 1
pinlabel=SELECT
T 3600 4200 5 8 0 0 0 0 1
pintype=io
}
V 1000 4200 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 1000 3800 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 1000 3400 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 0 4600 8 10 1 1 0 0 1
refdes=SPI?
T 1500 3000 8 10 1 1 0 0 1
net=SCK:4
T 1500 3398 8 10 1 1 0 0 1
net=MOSI:3
T 1500 3796 8 10 1 1 0 0 1
net=MISO:2
B 0 1300 1100 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1000 1500 1300 1500 1 0 1
{
T 900 1600 5 6 1 1 0 0 1
pinnumber=7
T 2800 1500 5 8 0 0 0 0 1
pinseq=7
T 800 1500 9 10 1 1 0 6 1
pinlabel=GND
T 3600 1500 5 8 0 0 0 0 1
pintype=io
T 4400 1500 5 10 0 0 0 0 1
netname=GND
}
V 1000 3000 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 1000 1500 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 0 2300 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1000 2500 1300 2500 1 0 1
{
T 900 2600 5 6 1 1 0 0 1
pinnumber=5
T 2800 2500 5 8 0 0 0 0 1
pinseq=5
T 800 2500 9 10 1 1 0 6 1
pinlabel=XTALO
T 3600 2500 5 8 0 0 0 0 1
pintype=io
T 4400 2500 5 10 0 0 0 0 1
netname=VCC
}
V 1000 2500 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1500 1496 8 10 1 1 0 0 1
net=GND:7
B 0 0 1100 1300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1000 1000 1300 1000 1 0 1
{
T 900 1100 5 6 1 1 0 0 1
pinnumber=8
T 2800 1000 5 8 0 0 0 0 1
pinseq=8
T 800 1000 9 10 1 1 0 6 1
pinlabel=XDCS
T 3600 1000 5 8 0 0 0 0 1
pintype=io
T 4400 1000 5 10 0 0 0 0 1
netname=VCC
}
P 1000 600 1300 600 1 0 1
{
T 900 700 5 6 1 1 0 0 1
pinnumber=9
T 2800 600 5 8 0 0 0 0 1
pinseq=9
T 800 600 9 10 1 1 0 6 1
pinlabel=DREQ
T 3600 600 5 8 0 0 0 0 1
pintype=io
T 4400 600 5 10 0 0 0 0 1
netname=GND
}
V 1000 1000 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 1000 600 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1500 596 8 10 1 1 0 0 1
net=VS_DREQ:9
T 1500 996 8 10 1 1 0 0 1
net=VS_XDCS:8
P 1000 200 1300 200 1 0 1
{
T 900 300 5 6 1 1 0 0 1
pinnumber=10
T 2800 200 5 8 0 0 0 0 1
pinseq=10
T 800 200 9 10 1 1 0 6 1
pinlabel=DREQ
T 3600 200 5 8 0 0 0 0 1
pintype=io
T 4400 200 5 10 0 0 0 0 1
netname=GND
}
V 1000 200 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1500 196 8 10 1 1 0 0 1
net=VS_RESET:10
T 1500 2496 8 10 1 1 0 0 1
net=XTALO:5
P 1000 1900 1300 1900 1 0 1
{
T 900 2000 5 6 1 1 0 0 1
pinnumber=6
T 2800 1900 5 8 0 0 0 0 1
pinseq=6
T 800 1900 9 10 1 1 0 6 1
pinlabel=VCC
T 3600 1900 5 8 0 0 0 0 1
pintype=io
T 4400 1900 5 10 0 0 0 0 1
netname=VCC
}
T 1500 1896 8 10 1 1 0 0 1
net=VCC:6
V 1000 1900 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1