v 20031231 1
P 0 400 300 400 1 0 0
{
T 200 450 5 8 1 1 0 6 1
pinnumber=1
T 200 350 5 8 0 1 0 8 1
pinseq=1
T 350 400 5 8 0 1 0 2 1
pintype=in
T 350 400 9 8 0 1 0 0 1
pinlabel=A
}
P 0 800 300 800 1 0 0
{
T 200 850 5 8 1 1 0 6 1
pinnumber=2
T 200 750 5 8 0 1 0 8 1
pinseq=2
T 350 800 5 8 0 1 0 2 1
pintype=in
T 350 800 9 8 0 1 0 0 1
pinlabel=B
}
L 300 1000 300 200 3 0 0 0 -1 -1
L 300 1000 1100 1000 3 0 0 0 -1 -1
L 300 200 1100 200 3 0 0 0 -1 -1
A 1100 600 400 270 180 3 0 0 0 -1 -1
P 1600 600 1800 600 1 0 1
{
T 1600 650 5 8 1 1 0 0 1
pinnumber=3
T 1600 550 5 8 0 1 0 2 1
pinseq=3
T 1450 600 5 8 0 1 0 8 1
pintype=out
T 1450 600 9 8 0 1 0 6 1
pinlabel=Y
}
T 2400 0 5 10 0 0 0 0 1
net=VDD:8
T 2400 200 5 10 0 0 0 0 1
net=VSS:4
T 2400 400 5 10 0 0 0 0 1
device=40107
T 2400 800 5 10 0 0 0 0 1
numslots=2
T 2400 1000 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 2400 1200 5 10 0 0 0 0 1
slotdef=2:7,6,5
V 1550 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 300 1100 8 10 1 1 0 0 1
refdes=U?
T 2400 600 5 10 0 0 0 0 1
slot=1
T 2400 1400 5 10 0 0 0 0 1
footprint=DIP8
T 2400 1600 5 10 0 0 0 0 1
description=2 AND gates with 2 inputs
T 300 0 9 10 1 0 0 0 1
40107