v 20050820 1 L 300 600 300 200 3 12 0 0 -1 -1 T 700 800 5 10 0 0 0 0 1 device=NMOS_TRANSISTOR L 200 600 200 200 3 12 0 0 -1 -1 L 300 600 500 600 3 12 0 0 -1 -1 L 300 200 500 200 3 12 0 0 -1 -1 L 300 400 500 400 3 12 0 0 -1 -1 L 300 400 400 500 3 12 0 0 -1 -1 L 300 400 400 300 3 12 0 0 -1 -1 P 0 400 200 400 1 0 0 { T 150 450 5 8 0 1 0 6 1 pinnumber=G T 150 350 5 8 0 1 0 8 1 pinseq=2 T 200 400 9 8 0 1 0 0 1 pinlabel=G T 200 400 5 8 0 1 0 2 1 pintype=in } P 500 600 500 800 1 0 1 { T 550 650 5 8 0 1 0 0 1 pinnumber=D T 550 650 5 8 0 1 0 2 1 pinseq=1 T 500 600 9 8 0 1 0 5 1 pinlabel=D T 500 400 5 8 0 1 0 5 1 pintype=pas } P 500 400 700 400 1 0 1 { T 550 450 5 8 0 1 0 0 1 pinnumber=B T 550 350 5 8 0 1 0 2 1 pinseq=4 T 500 400 9 8 0 1 0 6 1 pinlabel=B T 500 400 5 8 0 1 0 8 1 pintype=pas } P 500 200 500 0 1 0 1 { T 550 50 5 8 0 1 0 0 1 pinnumber=S T 550 50 5 8 0 1 0 2 1 pinseq=3 T 500 200 9 8 0 1 0 3 1 pinlabel=S T 500 500 5 8 0 1 0 3 1 pintype=pas } T 700 600 8 10 1 1 0 0 1 refdes=Q? T 700 1400 5 10 0 0 0 0 1 description=NMOS transistor T 700 1200 5 10 0 0 0 0 1 numslots=0 T 700 1000 5 10 0 0 0 0 1 symversion=0.1