v 20130411 1
P 100 20400 400 20400 1 0 0
{
T 300 20450 5 8 1 1 0 6 1
pinnumber=23
T 300 20350 5 8 0 1 0 8 1
pinseq=1
T 450 20400 9 8 1 1 0 0 1
pinlabel=PA0-WKUP/USART2_CTS/UART4_TX/ETH_MII_CRS/TIM2_CH1_ETR/WKUP/TIM5_CH1/TIM8_ETR/ADC123_IN0
T 450 20400 5 8 0 1 0 2 1
pintype=io
}
P 100 20000 400 20000 1 0 0
{
T 300 20050 5 8 1 1 0 6 1
pinnumber=24
T 300 19950 5 8 0 1 0 8 1
pinseq=2
T 450 20000 9 8 1 1 0 0 1
pinlabel=PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIMM2_CH2/ADC123_IN1
T 450 20000 5 8 0 1 0 2 1
pintype=io
}
P 100 19600 400 19600 1 0 0
{
T 300 19650 5 8 1 1 0 6 1
pinnumber=25
T 300 19550 5 8 0 1 0 8 1
pinseq=3
T 450 19600 9 8 1 1 0 0 1
pinlabel=PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/ADC123_IN2
T 450 19600 5 8 0 1 0 2 1
pintype=io
}
P 100 19200 400 19200 1 0 0
{
T 300 19250 5 8 1 1 0 6 1
pinnumber=26
T 300 19150 5 8 0 1 0 8 1
pinseq=4
T 450 19200 9 8 1 1 0 0 1
pinlabel=PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/ADC123_IN3
T 450 19200 5 8 0 1 0 2 1
pintype=io
}
P 100 18800 400 18800 1 0 0
{
T 300 18850 5 8 1 1 0 6 1
pinnumber=29
T 300 18750 5 8 0 1 0 8 1
pinseq=5
T 450 18800 9 8 1 1 0 0 1
pinlabel=PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/DAC1_OUT/OTG_HS_SOF/I2S3_WS/ADC12_IN4
T 450 18800 5 8 0 1 0 2 1
pintype=io
}
P 100 18400 400 18400 1 0 0
{
T 300 18450 5 8 1 1 0 6 1
pinnumber=30
T 300 18350 5 8 0 1 0 8 1
pinseq=6
T 450 18400 9 8 1 1 0 0 1
pinlabel=PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/DAC2_OUT/TIM8_CHIN/ADC12_IN5
T 450 18400 5 8 0 1 0 2 1
pintype=io
}
P 100 18000 400 18000 1 0 0
{
T 300 18050 5 8 1 1 0 6 1
pinnumber=31
T 300 17950 5 8 0 1 0 8 1
pinseq=7
T 450 18000 9 8 1 1 0 0 1
pinlabel=PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/ADC12_IN6
T 450 18000 5 8 0 1 0 2 1
pintype=io
}
P 100 17600 400 17600 1 0 0
{
T 300 17650 5 8 1 1 0 6 1
pinnumber=32
T 300 17550 5 8 0 1 0 8 1
pinseq=8
T 450 17600 9 8 1 1 0 0 1
pinlabel=PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/RMII_CRS_DV/ADC12_IN7
T 450 17600 5 8 0 1 0 2 1
pintype=io
}
P 100 17200 400 17200 1 0 0
{
T 300 17250 5 8 1 1 0 6 1
pinnumber=67
T 300 17150 5 8 0 1 0 8 1
pinseq=9
T 450 17200 9 8 1 1 0 0 1
pinlabel=PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF
T 450 17200 5 8 0 1 0 2 1
pintype=io
}
P 100 16800 400 16800 1 0 0
{
T 300 16850 5 8 1 1 0 6 1
pinnumber=68
T 300 16750 5 8 0 1 0 8 1
pinseq=10
T 450 16800 9 8 1 1 0 0 1
pinlabel=PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/OTG_FS_VBUS
T 450 16800 5 8 0 1 0 2 1
pintype=io
}
P 100 16400 400 16400 1 0 0
{
T 300 16450 5 8 1 1 0 6 1
pinnumber=69
T 300 16350 5 8 0 1 0 8 1
pinseq=11
T 450 16400 9 8 1 1 0 0 1
pinlabel=PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1
T 450 16400 5 8 0 1 0 2 1
pintype=io
}
P 100 16000 400 16000 1 0 0
{
T 300 16050 5 8 1 1 0 6 1
pinnumber=70
T 300 15950 5 8 0 1 0 8 1
pinseq=12
T 450 16000 9 8 1 1 0 0 1
pinlabel=PA11/USART1_CTS/CAN1_RX/TIM1_CH4/OTG_FS_DM
T 450 16000 5 8 0 1 0 2 1
pintype=io
}
P 100 15600 400 15600 1 0 0
{
T 300 15650 5 8 1 1 0 6 1
pinnumber=71
T 300 15550 5 8 0 1 0 8 1
pinseq=13
T 450 15600 9 8 1 1 0 0 1
pinlabel=PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP
T 450 15600 5 8 0 1 0 2 1
pintype=io
}
P 100 15200 400 15200 1 0 0
{
T 300 15250 5 8 1 1 0 6 1
pinnumber=72
T 300 15150 5 8 0 1 0 8 1
pinseq=14
T 450 15200 9 8 1 1 0 0 1
pinlabel=PA13/JTMS-SWDIO
T 450 15200 5 8 0 1 0 2 1
pintype=io
}
P 100 14800 400 14800 1 0 0
{
T 300 14850 5 8 1 1 0 6 1
pinnumber=76
T 300 14750 5 8 0 1 0 8 1
pinseq=15
T 450 14800 9 8 1 1 0 0 1
pinlabel=PA14/JTCK-SWCLK
T 450 14800 5 8 0 1 0 2 1
pintype=io
}
P 100 14400 400 14400 1 0 0
{
T 300 14450 5 8 1 1 0 6 1
pinnumber=77
T 300 14350 5 8 0 1 0 8 1
pinseq=16
T 450 14400 9 8 1 1 0 0 1
pinlabel=PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS
T 450 14400 5 8 0 1 0 2 1
pintype=io
}
P 100 13600 400 13600 1 0 0
{
T 300 13650 5 8 1 1 0 6 1
pinnumber=35
T 300 13550 5 8 0 1 0 8 1
pinseq=17
T 450 13600 9 8 1 1 0 0 1
pinlabel=PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/ADC12_IN8
T 450 13600 5 8 0 1 0 2 1
pintype=io
}
P 100 13200 400 13200 1 0 0
{
T 300 13250 5 8 1 1 0 6 1
pinnumber=36
T 300 13150 5 8 0 1 0 8 1
pinseq=18
T 450 13200 9 8 1 1 0 0 1
pinlabel=PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/TIM1_CH3N/ADC12_IN9
T 450 13200 5 8 0 1 0 2 1
pintype=io
}
P 100 12800 400 12800 1 0 0
{
T 300 12850 5 8 1 1 0 6 1
pinnumber=37
T 300 12750 5 8 0 1 0 8 1
pinseq=19
T 450 12800 9 8 1 1 0 0 1
pinlabel=PB2-BOOT1
T 450 12800 5 8 0 1 0 2 1
pintype=io
}
P 100 12400 400 12400 1 0 0
{
T 300 12450 5 8 1 1 0 6 1
pinnumber=89
T 300 12350 5 8 0 1 0 8 1
pinseq=20
T 450 12400 9 8 1 1 0 0 1
pinlabel=PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK
T 450 12400 5 8 0 1 0 2 1
pintype=io
}
P 100 12000 400 12000 1 0 0
{
T 300 12050 5 8 1 1 0 6 1
pinnumber=90
T 300 11950 5 8 0 1 0 8 1
pinseq=21
T 450 12000 9 8 1 1 0 0 1
pinlabel=PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD
T 450 12000 5 8 0 1 0 2 1
pintype=io
}
P 100 11600 400 11600 1 0 0
{
T 300 11650 5 8 1 1 0 6 1
pinnumber=91
T 300 11550 5 8 0 1 0 8 1
pinseq=22
T 450 11600 9 8 1 1 0 0 1
pinlabel=PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH/2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD
T 450 11600 5 8 0 1 0 2 1
pintype=io
}
P 100 11200 400 11200 1 0 0
{
T 300 11250 5 8 1 1 0 6 1
pinnumber=92
T 300 11150 5 8 0 1 0 8 1
pinseq=23
T 450 11200 9 8 1 1 0 0 1
pinlabel=PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX
T 450 11200 5 8 0 1 0 2 1
pintype=io
}
P 100 10800 400 10800 1 0 0
{
T 300 10850 5 8 1 1 0 6 1
pinnumber=93
T 300 10750 5 8 0 1 0 8 1
pinseq=24
T 450 10800 9 8 1 1 0 0 1
pinlabel=PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2
T 450 10800 5 8 0 1 0 2 1
pintype=io
}
P 100 10400 400 10400 1 0 0
{
T 300 10450 5 8 1 1 0 6 1
pinnumber=95
T 300 10350 5 8 0 1 0 8 1
pinseq=25
T 450 10400 9 8 1 1 0 0 1
pinlabel=PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX
T 450 10400 5 8 0 1 0 2 1
pintype=io
}
P 100 10000 400 10000 1 0 0
{
T 300 10050 5 8 1 1 0 6 1
pinnumber=96
T 300 9950 5 8 0 1 0 8 1
pinseq=26
T 450 10000 9 8 1 1 0 0 1
pinlabel=PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX
T 450 10000 5 8 0 1 0 2 1
pintype=io
}
P 100 9600 400 9600 1 0 0
{
T 300 9650 5 8 1 1 0 6 1
pinnumber=47
T 300 9550 5 8 0 1 0 8 1
pinseq=27
T 450 9600 9 8 1 1 0 0 1
pinlabel=PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3
T 450 9600 5 8 0 1 0 2 1
pintype=io
}
P 100 9200 400 9200 1 0 0
{
T 300 9250 5 8 1 1 0 6 1
pinnumber=48
T 300 9150 5 8 0 1 0 8 1
pinseq=28
T 450 9200 9 8 1 1 0 0 1
pinlabel=PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4
T 450 9200 5 8 0 1 0 2 1
pintype=io
}
P 100 8800 400 8800 1 0 0
{
T 300 8850 5 8 1 1 0 6 1
pinnumber=51
T 300 8750 5 8 0 1 0 8 1
pinseq=29
T 450 8800 9 8 1 1 0 0 1
pinlabel=PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID
T 450 8800 5 8 0 1 0 2 1
pintype=io
}
P 100 8400 400 8400 1 0 0
{
T 300 8450 5 8 1 1 0 6 1
pinnumber=52
T 300 8350 5 8 0 1 0 8 1
pinseq=30
T 450 8400 9 8 1 1 0 0 1
pinlabel=PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/OTG_HS_VBUS/ETH_RMII_TXD1/ETH_MII_TXD1
T 450 8400 5 8 0 1 0 2 1
pintype=io
}
P 100 8000 400 8000 1 0 0
{
T 300 8050 5 8 1 1 0 6 1
pinnumber=53
T 300 7950 5 8 0 1 0 8 1
pinseq=31
T 450 8000 9 8 1 1 0 0 1
pinlabel=PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD
T 450 8000 5 8 0 1 0 2 1
pintype=io
}
P 100 7600 400 7600 1 0 0
{
T 300 7650 5 8 1 1 0 6 1
pinnumber=54
T 300 7550 5 8 0 1 0 8 1
pinseq=32
T 450 7600 9 8 1 1 0 0 1
pinlabel=PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP
T 450 7600 5 8 0 1 0 2 1
pintype=io
}
P 100 6800 400 6800 1 0 0
{
T 300 6850 5 8 1 1 0 6 1
pinnumber=15
T 300 6750 5 8 0 1 0 8 1
pinseq=33
T 450 6800 9 8 1 1 0 0 1
pinlabel=PC0/OTG_HS_ULPI_STP/ADC123_IN10
T 450 6800 5 8 0 1 0 2 1
pintype=io
}
P 100 6400 400 6400 1 0 0
{
T 300 6450 5 8 1 1 0 6 1
pinnumber=16
T 300 6350 5 8 0 1 0 8 1
pinseq=34
T 450 6400 9 8 1 1 0 0 1
pinlabel=PC1/ETH_MDC/ADC123_IN11
T 450 6400 5 8 0 1 0 2 1
pintype=io
}
P 100 6000 400 6000 1 0 0
{
T 300 6050 5 8 1 1 0 6 1
pinnumber=17
T 300 5950 5 8 0 1 0 8 1
pinseq=35
T 450 6000 9 8 1 1 0 0 1
pinlabel=PC2/SPI2_MISO/OTG_HS_ULPI_DIR/TH_MII_TXD2/I2S2ext_SD/ADC123_IN12
T 450 6000 5 8 0 1 0 2 1
pintype=io
}
P 100 5600 400 5600 1 0 0
{
T 300 5650 5 8 1 1 0 6 1
pinnumber=18
T 300 5550 5 8 0 1 0 8 1
pinseq=36
T 450 5600 9 8 1 1 0 0 1
pinlabel=PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/ADC123_IN13
T 450 5600 5 8 0 1 0 2 1
pintype=io
}
P 100 5200 400 5200 1 0 0
{
T 300 5250 5 8 1 1 0 6 1
pinnumber=33
T 300 5150 5 8 0 1 0 8 1
pinseq=37
T 450 5200 9 8 1 1 0 0 1
pinlabel=PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/ADC12_IN14
T 450 5200 5 8 0 1 0 2 1
pintype=io
}
P 100 4800 400 4800 1 0 0
{
T 300 4850 5 8 1 1 0 6 1
pinnumber=34
T 300 4750 5 8 0 1 0 8 1
pinseq=38
T 450 4800 9 8 1 1 0 0 1
pinlabel=PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/ADC12_IN15
T 450 4800 5 8 0 1 0 2 1
pintype=io
}
P 100 4400 400 4400 1 0 0
{
T 300 4450 5 8 1 1 0 6 1
pinnumber=63
T 300 4350 5 8 0 1 0 8 1
pinseq=39
T 450 4400 9 8 1 1 0 0 1
pinlabel=PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1
T 450 4400 5 8 0 1 0 2 1
pintype=io
}
P 100 4000 400 4000 1 0 0
{
T 300 4050 5 8 1 1 0 6 1
pinnumber=64
T 300 3950 5 8 0 1 0 8 1
pinseq=40
T 450 4000 9 8 1 1 0 0 1
pinlabel=PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2
T 450 4000 5 8 0 1 0 2 1
pintype=io
}
P 100 3600 400 3600 1 0 0
{
T 300 3650 5 8 1 1 0 6 1
pinnumber=65
T 300 3550 5 8 0 1 0 8 1
pinseq=41
T 450 3600 9 8 1 1 0 0 1
pinlabel=PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2
T 450 3600 5 8 0 1 0 2 1
pintype=io
}
P 100 3200 400 3200 1 0 0
{
T 300 3250 5 8 1 1 0 6 1
pinnumber=66
T 300 3150 5 8 0 1 0 8 1
pinseq=42
T 450 3200 9 8 1 1 0 0 1
pinlabel=PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/DCMI_D3/TIM3_CH4
T 450 3200 5 8 0 1 0 2 1
pintype=io
}
P 100 2800 400 2800 1 0 0
{
T 300 2850 5 8 1 1 0 6 1
pinnumber=78
T 300 2750 5 8 0 1 0 8 1
pinseq=43
T 450 2800 9 8 1 1 0 0 1
pinlabel=PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX
T 450 2800 5 8 0 1 0 2 1
pintype=io
}
P 100 2400 400 2400 1 0 0
{
T 300 2450 5 8 1 1 0 6 1
pinnumber=79
T 300 2350 5 8 0 1 0 8 1
pinseq=44
T 450 2400 9 8 1 1 0 0 1
pinlabel=PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD
T 450 2400 5 8 0 1 0 2 1
pintype=io
}
P 100 2000 400 2000 1 0 0
{
T 300 2050 5 8 1 1 0 6 1
pinnumber=80
T 300 1950 5 8 0 1 0 8 1
pinseq=45
T 450 2000 9 8 1 1 0 0 1
pinlabel=PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK
T 450 2000 5 8 0 1 0 2 1
pintype=io
}
P 100 1600 400 1600 1 0 0
{
T 300 1650 5 8 1 1 0 6 1
pinnumber=7
T 300 1550 5 8 0 1 0 8 1
pinseq=46
T 450 1600 9 8 1 1 0 0 1
pinlabel=PC13/RTC_AF1
T 450 1600 5 8 0 1 0 2 1
pintype=io
}
P 100 1200 400 1200 1 0 0
{
T 300 1250 5 8 1 1 0 6 1
pinnumber=8
T 300 1150 5 8 0 1 0 8 1
pinseq=47
T 450 1200 9 8 1 1 0 0 1
pinlabel=PC14-OSC32_IN
T 450 1200 5 8 0 1 0 2 1
pintype=io
}
P 100 800 400 800 1 0 0
{
T 300 850 5 8 1 1 0 6 1
pinnumber=9
T 300 750 5 8 0 1 0 8 1
pinseq=48
T 450 800 9 8 1 1 0 0 1
pinlabel=PC15-OSC32_OUT
T 450 800 5 8 0 1 0 2 1
pintype=io
}
P 12200 20400 11900 20400 1 0 0
{
T 12000 20450 5 8 1 1 0 0 1
pinnumber=81
T 12000 20350 5 8 0 1 0 2 1
pinseq=49
T 11850 20400 9 8 1 1 0 6 1
pinlabel=PD0/FSMC_D2/CAN1_RX
T 11850 20400 5 8 0 1 0 8 1
pintype=io
}
P 12200 20000 11900 20000 1 0 0
{
T 12000 20050 5 8 1 1 0 0 1
pinnumber=82
T 12000 19950 5 8 0 1 0 2 1
pinseq=50
T 11850 20000 9 8 1 1 0 6 1
pinlabel=PD1/FSMC_D3/CAN1_TX
T 11850 20000 5 8 0 1 0 8 1
pintype=io
}
P 12200 19600 11900 19600 1 0 0
{
T 12000 19650 5 8 1 1 0 0 1
pinnumber=83
T 12000 19550 5 8 0 1 0 2 1
pinseq=51
T 11850 19600 9 8 1 1 0 6 1
pinlabel=PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11
T 11850 19600 5 8 0 1 0 8 1
pintype=io
}
P 12200 19200 11900 19200 1 0 0
{
T 12000 19250 5 8 1 1 0 0 1
pinnumber=84
T 12000 19150 5 8 0 1 0 2 1
pinseq=52
T 11850 19200 9 8 1 1 0 6 1
pinlabel=PD3/FSMC_CLK/USART2_CTS
T 11850 19200 5 8 0 1 0 8 1
pintype=io
}
P 12200 18800 11900 18800 1 0 0
{
T 12000 18850 5 8 1 1 0 0 1
pinnumber=85
T 12000 18750 5 8 0 1 0 2 1
pinseq=53
T 11850 18800 9 8 1 1 0 6 1
pinlabel=PD4/FSMC_NOE/USART2_RTS
T 11850 18800 5 8 0 1 0 8 1
pintype=io
}
P 12200 18400 11900 18400 1 0 0
{
T 12000 18450 5 8 1 1 0 0 1
pinnumber=86
T 12000 18350 5 8 0 1 0 2 1
pinseq=54
T 11850 18400 9 8 1 1 0 6 1
pinlabel=PD5/FSMC_NWE/USART2_TX
T 11850 18400 5 8 0 1 0 8 1
pintype=io
}
P 12200 18000 11900 18000 1 0 0
{
T 12000 18050 5 8 1 1 0 0 1
pinnumber=87
T 12000 17950 5 8 0 1 0 2 1
pinseq=55
T 11850 18000 9 8 1 1 0 6 1
pinlabel=PD6/FSMC_NWAIT/USART2_RX
T 11850 18000 5 8 0 1 0 8 1
pintype=io
}
P 12200 17600 11900 17600 1 0 0
{
T 12000 17650 5 8 1 1 0 0 1
pinnumber=88
T 12000 17550 5 8 0 1 0 2 1
pinseq=56
T 11850 17600 9 8 1 1 0 6 1
pinlabel=PD7/USART2_CK/FSMC_NE1/FSMC_NCE2
T 11850 17600 5 8 0 1 0 8 1
pintype=io
}
P 12200 17200 11900 17200 1 0 0
{
T 12000 17250 5 8 1 1 0 0 1
pinnumber=55
T 12000 17150 5 8 0 1 0 2 1
pinseq=57
T 11850 17200 9 8 1 1 0 6 1
pinlabel=PD8/FSMC_D13/USART3_TX
T 11850 17200 5 8 0 1 0 8 1
pintype=io
}
P 12200 16800 11900 16800 1 0 0
{
T 12000 16850 5 8 1 1 0 0 1
pinnumber=56
T 12000 16750 5 8 0 1 0 2 1
pinseq=58
T 11850 16800 9 8 1 1 0 6 1
pinlabel=PD9/FSMC_D14/USART3_RX
T 11850 16800 5 8 0 1 0 8 1
pintype=io
}
P 12200 16400 11900 16400 1 0 0
{
T 12000 16450 5 8 1 1 0 0 1
pinnumber=57
T 12000 16350 5 8 0 1 0 2 1
pinseq=59
T 11850 16400 9 8 1 1 0 6 1
pinlabel=PD10/FSMC_D15/USART3_CK
T 11850 16400 5 8 0 1 0 8 1
pintype=io
}
P 12200 16000 11900 16000 1 0 0
{
T 12000 16050 5 8 1 1 0 0 1
pinnumber=58
T 12000 15950 5 8 0 1 0 2 1
pinseq=60
T 11850 16000 9 8 1 1 0 6 1
pinlabel=PD11/FSMC_CLE/FSMC_A16/USART3_CTS
T 11850 16000 5 8 0 1 0 8 1
pintype=io
}
P 12200 15600 11900 15600 1 0 0
{
T 12000 15650 5 8 1 1 0 0 1
pinnumber=59
T 12000 15550 5 8 0 1 0 2 1
pinseq=61
T 11850 15600 9 8 1 1 0 6 1
pinlabel=PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS
T 11850 15600 5 8 0 1 0 8 1
pintype=io
}
P 12200 15200 11900 15200 1 0 0
{
T 12000 15250 5 8 1 1 0 0 1
pinnumber=60
T 12000 15150 5 8 0 1 0 2 1
pinseq=62
T 11850 15200 9 8 1 1 0 6 1
pinlabel=PD13/FSMC_A18/TIM4_CH2
T 11850 15200 5 8 0 1 0 8 1
pintype=io
}
P 12200 14800 11900 14800 1 0 0
{
T 12000 14850 5 8 1 1 0 0 1
pinnumber=61
T 12000 14750 5 8 0 1 0 2 1
pinseq=63
T 11850 14800 9 8 1 1 0 6 1
pinlabel=PD14/FSMC_D0/TIM4_CH3/EVENTOUT
T 11850 14800 5 8 0 1 0 8 1
pintype=io
}
P 12200 14400 11900 14400 1 0 0
{
T 12000 14450 5 8 1 1 0 0 1
pinnumber=62
T 12000 14350 5 8 0 1 0 2 1
pinseq=64
T 11850 14400 9 8 1 1 0 6 1
pinlabel=PD15/FSMC_D1/TIM4_CH4
T 11850 14400 5 8 0 1 0 8 1
pintype=io
}
P 12200 13600 11900 13600 1 0 0
{
T 12000 13650 5 8 1 1 0 0 1
pinnumber=97
T 12000 13550 5 8 0 1 0 2 1
pinseq=65
T 11850 13600 9 8 1 1 0 6 1
pinlabel=PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2
T 11850 13600 5 8 0 1 0 8 1
pintype=io
}
P 12200 13200 11900 13200 1 0 0
{
T 12000 13250 5 8 1 1 0 0 1
pinnumber=98
T 12000 13150 5 8 0 1 0 2 1
pinseq=66
T 11850 13200 9 8 1 1 0 6 1
pinlabel=PE1/FSMC_NBL1/DCMI_D3
T 11850 13200 5 8 0 1 0 8 1
pintype=io
}
P 12200 12800 11900 12800 1 0 0
{
T 12000 12850 5 8 1 1 0 0 1
pinnumber=1
T 12000 12750 5 8 0 1 0 2 1
pinseq=67
T 11850 12800 9 8 1 1 0 6 1
pinlabel=PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3
T 11850 12800 5 8 0 1 0 8 1
pintype=io
}
P 12200 12400 11900 12400 1 0 0
{
T 12000 12450 5 8 1 1 0 0 1
pinnumber=2
T 12000 12350 5 8 0 1 0 2 1
pinseq=68
T 11850 12400 9 8 1 1 0 6 1
pinlabel=PE3/TRACED0/FSMC_A19
T 11850 12400 5 8 0 1 0 8 1
pintype=io
}
P 12200 12000 11900 12000 1 0 0
{
T 12000 12050 5 8 1 1 0 0 1
pinnumber=3
T 12000 11950 5 8 0 1 0 2 1
pinseq=69
T 11850 12000 9 8 1 1 0 6 1
pinlabel=PE4/TRACED1/FSMC_A20/DCMI_D4
T 11850 12000 5 8 0 1 0 8 1
pintype=io
}
P 12200 11600 11900 11600 1 0 0
{
T 12000 11650 5 8 1 1 0 0 1
pinnumber=4
T 12000 11550 5 8 0 1 0 2 1
pinseq=70
T 11850 11600 9 8 1 1 0 6 1
pinlabel=PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6
T 11850 11600 5 8 0 1 0 8 1
pintype=io
}
P 12200 11200 11900 11200 1 0 0
{
T 12000 11250 5 8 1 1 0 0 1
pinnumber=5
T 12000 11150 5 8 0 1 0 2 1
pinseq=71
T 11850 11200 9 8 1 1 0 6 1
pinlabel=PE6/TRACED3/FSMC_A22/TIM9_CH2/DCMI_D7
T 11850 11200 5 8 0 1 0 8 1
pintype=io
}
P 12200 10800 11900 10800 1 0 0
{
T 12000 10850 5 8 1 1 0 0 1
pinnumber=38
T 12000 10750 5 8 0 1 0 2 1
pinseq=72
T 11850 10800 9 8 1 1 0 6 1
pinlabel=PE7/FSMC_D4/TIM1_ETR
T 11850 10800 5 8 0 1 0 8 1
pintype=io
}
P 12200 10400 11900 10400 1 0 0
{
T 12000 10450 5 8 1 1 0 0 1
pinnumber=39
T 12000 10350 5 8 0 1 0 2 1
pinseq=73
T 11850 10400 9 8 1 1 0 6 1
pinlabel=PE8/FSMC_D5/TIM1_CH1N
T 11850 10400 5 8 0 1 0 8 1
pintype=io
}
P 12200 10000 11900 10000 1 0 0
{
T 12000 10050 5 8 1 1 0 0 1
pinnumber=40
T 12000 9950 5 8 0 1 0 2 1
pinseq=74
T 11850 10000 9 8 1 1 0 6 1
pinlabel=PE9/FSMC_D6/TIM1_CH1
T 11850 10000 5 8 0 1 0 8 1
pintype=io
}
P 12200 9600 11900 9600 1 0 0
{
T 12000 9650 5 8 1 1 0 0 1
pinnumber=41
T 12000 9550 5 8 0 1 0 2 1
pinseq=75
T 11850 9600 9 8 1 1 0 6 1
pinlabel=PE10/FSMC_D7/TIM1_CH2N
T 11850 9600 5 8 0 1 0 8 1
pintype=io
}
P 12200 9200 11900 9200 1 0 0
{
T 12000 9250 5 8 1 1 0 0 1
pinnumber=42
T 12000 9150 5 8 0 1 0 2 1
pinseq=76
T 11850 9200 9 8 1 1 0 6 1
pinlabel=PE11/FSMC_D8/TIM1_CH2
T 11850 9200 5 8 0 1 0 8 1
pintype=io
}
P 12200 8800 11900 8800 1 0 0
{
T 12000 8850 5 8 1 1 0 0 1
pinnumber=43
T 12000 8750 5 8 0 1 0 2 1
pinseq=77
T 11850 8800 9 8 1 1 0 6 1
pinlabel=PE12/FSMC_D9/TIM1_CH3N
T 11850 8800 5 8 0 1 0 8 1
pintype=io
}
P 12200 8400 11900 8400 1 0 0
{
T 12000 8450 5 8 1 1 0 0 1
pinnumber=44
T 12000 8350 5 8 0 1 0 2 1
pinseq=78
T 11850 8400 9 8 1 1 0 6 1
pinlabel=PE13/FSMC_D10/TIM1_CH3
T 11850 8400 5 8 0 1 0 8 1
pintype=io
}
P 12200 8000 11900 8000 1 0 0
{
T 12000 8050 5 8 1 1 0 0 1
pinnumber=45
T 12000 7950 5 8 0 1 0 2 1
pinseq=79
T 11850 8000 9 8 1 1 0 6 1
pinlabel=PE14/FSMC_D11/TIM1_CH4
T 11850 8000 5 8 0 1 0 8 1
pintype=io
}
P 12200 7600 11900 7600 1 0 0
{
T 12000 7650 5 8 1 1 0 0 1
pinnumber=46
T 12000 7550 5 8 0 1 0 2 1
pinseq=80
T 11850 7600 9 8 1 1 0 6 1
pinlabel=PE15/FSMC_D12/TIM1_BKIN
T 11850 7600 5 8 0 1 0 8 1
pintype=io
}
P 12200 6000 11900 6000 1 0 0
{
T 12000 6050 5 8 1 1 0 0 1
pinnumber=94
T 12000 5950 5 8 0 1 0 2 1
pinseq=81
T 11850 6000 9 8 1 1 0 6 1
pinlabel=BOOT0
T 11850 6000 5 8 0 1 0 8 1
pintype=in
}
P 12200 5600 11900 5600 1 0 0
{
T 12000 5650 5 8 1 1 0 0 1
pinnumber=14
T 12000 5550 5 8 0 1 0 2 1
pinseq=82
T 11850 5600 9 8 1 1 0 6 1
pinlabel=NRST
T 11850 5600 5 8 0 1 0 8 1
pintype=io
}
P 12200 4000 11900 4000 1 0 0
{
T 12000 4050 5 8 1 1 0 0 1
pinnumber=12
T 12000 3950 5 8 0 1 0 2 1
pinseq=83
T 11850 4000 9 8 1 1 0 6 1
pinlabel=PH0/OSC_IN
T 11850 4000 5 8 0 1 0 8 1
pintype=io
}
P 12200 3600 11900 3600 1 0 0
{
T 12000 3650 5 8 1 1 0 0 1
pinnumber=13
T 12000 3550 5 8 0 1 0 2 1
pinseq=84
T 11850 3600 9 8 1 1 0 6 1
pinlabel=PH1/OSC_OUT
T 11850 3600 5 8 0 1 0 8 1
pintype=io
}
P 12200 2000 11900 2000 1 0 0
{
T 12000 2050 5 8 1 1 0 0 1
pinnumber=6
T 12000 1950 5 8 0 1 0 2 1
pinseq=85
T 11850 2000 9 8 1 1 0 6 1
pinlabel=VBAT
T 11850 2000 5 8 0 1 0 8 1
pintype=pwr
}
P 12200 1600 11900 1600 1 0 0
{
T 12000 1650 5 8 1 1 0 0 1
pinnumber=49
T 12000 1550 5 8 0 1 0 2 1
pinseq=86
T 11850 1600 9 8 1 1 0 6 1
pinlabel=VCAP_1
T 11850 1600 5 8 0 1 0 8 1
pintype=pwr
}
P 12200 1200 11900 1200 1 0 0
{
T 12000 1250 5 8 1 1 0 0 1
pinnumber=73
T 12000 1150 5 8 0 1 0 2 1
pinseq=87
T 11850 1200 9 8 1 1 0 6 1
pinlabel=VCAP_2
T 11850 1200 5 8 0 1 0 8 1
pintype=pwr
}
P 4400 21100 4400 20800 1 0 0
{
T 4450 20900 5 8 1 1 0 0 1
pinnumber=11
T 4350 20900 5 8 0 1 0 6 1
pinseq=88
T 4400 20750 9 8 1 1 0 5 1
pinlabel=VDD
T 4400 20600 5 8 0 1 0 5 1
pintype=pwr
}
P 4800 21100 4800 20800 1 0 0
{
T 4850 20900 5 8 1 1 0 0 1
pinnumber=19
T 4750 20900 5 8 0 1 0 6 1
pinseq=89
T 4800 20750 9 8 1 1 0 5 1
pinlabel=VDD
T 4800 20600 5 8 0 1 0 5 1
pintype=pwr
}
P 5200 21100 5200 20800 1 0 0
{
T 5250 20900 5 8 1 1 0 0 1
pinnumber=28
T 5150 20900 5 8 0 1 0 6 1
pinseq=90
T 5200 20750 9 8 1 1 0 5 1
pinlabel=VDD
T 5200 20600 5 8 0 1 0 5 1
pintype=pwr
}
P 5600 21100 5600 20800 1 0 0
{
T 5650 20900 5 8 1 1 0 0 1
pinnumber=50
T 5550 20900 5 8 0 1 0 6 1
pinseq=91
T 5600 20750 9 8 1 1 0 5 1
pinlabel=VDD
T 5600 20600 5 8 0 1 0 5 1
pintype=pwr
}
P 6000 21100 6000 20800 1 0 0
{
T 6050 20900 5 8 1 1 0 0 1
pinnumber=75
T 5950 20900 5 8 0 1 0 6 1
pinseq=92
T 6000 20750 9 8 1 1 0 5 1
pinlabel=VDD
T 6000 20600 5 8 0 1 0 5 1
pintype=pwr
}
P 6400 21100 6400 20800 1 0 0
{
T 6450 20900 5 8 1 1 0 0 1
pinnumber=100
T 6350 20900 5 8 0 1 0 6 1
pinseq=93
T 6400 20750 9 8 1 1 0 5 1
pinlabel=VDD
T 6400 20600 5 8 0 1 0 5 1
pintype=pwr
}
P 7200 21100 7200 20800 1 0 0
{
T 7250 20900 5 8 1 1 0 0 1
pinnumber=22
T 7150 20900 5 8 0 1 0 6 1
pinseq=94
T 7200 20750 9 8 1 1 0 5 1
pinlabel=VDDA
T 7200 20600 5 8 0 1 0 5 1
pintype=pwr
}
P 8000 21100 8000 20800 1 0 0
{
T 8050 20900 5 8 1 1 0 0 1
pinnumber=21
T 7950 20900 5 8 0 1 0 6 1
pinseq=95
T 8000 20750 9 8 1 1 0 5 1
pinlabel=VREF+
T 8000 20600 5 8 0 1 0 5 1
pintype=pwr
}
P 5200 100 5200 400 1 0 0
{
T 5250 300 5 8 1 1 0 2 1
pinnumber=10
T 5150 300 5 8 0 1 0 8 1
pinseq=96
T 5200 450 9 8 1 1 0 3 1
pinlabel=VSS
T 5200 600 5 8 0 1 0 3 1
pintype=pwr
}
P 5600 100 5600 400 1 0 0
{
T 5650 300 5 8 1 1 0 2 1
pinnumber=27
T 5550 300 5 8 0 1 0 8 1
pinseq=97
T 5600 450 9 8 1 1 0 3 1
pinlabel=VSS
T 5600 600 5 8 0 1 0 3 1
pintype=pwr
}
P 6000 100 6000 400 1 0 0
{
T 6050 300 5 8 1 1 0 2 1
pinnumber=74
T 5950 300 5 8 0 1 0 8 1
pinseq=98
T 6000 450 9 8 1 1 0 3 1
pinlabel=VSS
T 6000 600 5 8 0 1 0 3 1
pintype=pwr
}
P 6400 100 6400 400 1 0 0
{
T 6450 300 5 8 1 1 0 2 1
pinnumber=99
T 6350 300 5 8 0 1 0 8 1
pinseq=99
T 6400 450 9 8 1 1 0 3 1
pinlabel=VSS
T 6400 600 5 8 0 1 0 3 1
pintype=pwr
}
P 7200 100 7200 400 1 0 0
{
T 7250 300 5 8 1 1 0 2 1
pinnumber=20
T 7150 300 5 8 0 1 0 8 1
pinseq=100
T 7200 450 9 8 1 1 0 3 1
pinlabel=VSSA
T 7200 600 5 8 0 1 0 3 1
pintype=pwr
}
B 400 400 11500 20400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 11900 20900 8 10 1 1 0 6 1
refdes=U?
T 5950 10500 9 10 1 0 0 0 1
STM32F407VXTY
T 5950 10800 5 10 0 0 0 0 1
device=STM32F407VXTY
T 5950 11000 5 10 0 0 0 0 1
footprint=LQFP100_14
T 5950 11200 5 10 0 0 0 0 1
author=Evgeny Ivanov
T 5950 11400 5 10 0 0 0 0 1
documentation=http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1577/LN11
T 5950 11600 5 10 0 0 0 0 1
description=STM32F407VXTY MCU
T 5950 11800 5 10 0 0 0 0 1
numslots=0
T 5950 12000 5 10 0 0 0 0 1
dist-license=GPL
T 5950 12200 5 10 0 0 0 0 1
use-license=unlimited
T 5950 12400 5 10 0 0 0 0 1
comment=generated with tragesym