v 20081231 1
L 500 800 700 700 3 0 0 0 -1 -1
L 700 700 500 600 3 0 0 0 -1 -1
L 500 800 500 600 3 0 0 0 -1 -1
L 700 600 500 500 3 0 0 0 -1 -1
L 500 500 700 400 3 0 0 0 -1 -1
L 700 600 700 400 3 0 0 0 -1 -1
L 300 900 900 900 3 0 0 0 -1 -1
L 900 900 900 300 3 0 0 0 -1 -1
L 900 300 300 300 3 0 0 0 -1 -1
L 300 300 300 900 3 0 0 0 -1 -1
L 500 700 400 700 3 0 0 0 -1 -1
L 500 500 400 500 3 0 0 0 -1 -1
L 400 700 400 500 3 0 0 0 -1 -1
L 700 700 800 700 3 0 0 0 -1 -1
L 700 500 800 500 3 0 0 0 -1 -1
L 800 700 800 500 3 0 0 0 -1 -1
L 800 600 900 600 3 0 0 0 -1 -1
L 400 600 300 600 3 0 0 0 -1 -1
P 1200 600 900 600 1 0 0
{
T 1200 600 5 10 0 0 0 0 1
pintype=io
T 945 395 9 8 0 1 0 0 1
pinlabel=B
T 995 645 5 8 1 1 0 0 1
pinnumber=4
T 1200 600 5 10 0 0 0 0 1
pinseq=1
}
P 0 600 300 600 1 0 0
{
T 0 600 5 10 0 0 0 0 1
pintype=io
T 255 395 9 8 0 1 0 6 1
pinlabel=A
T 205 645 5 8 1 1 0 6 1
pinnumber=3
T 0 600 5 10 0 0 0 0 1
pinseq=2
}
P 600 0 600 300 1 0 0
{
T 600 0 5 10 0 0 0 0 1
pintype=io
T 600 355 5 10 0 1 90 0 1
pinlabel=DIR
T 495 250 5 8 1 1 180 6 1
pinnumber=5
T 600 0 5 10 0 0 0 0 1
pinseq=3
}
T 700 100 9 8 1 0 0 0 1
74LVC1T45
T 995 1000 5 10 1 1 0 6 1
refdes=U?
T -1405 -1700 8 10 0 1 0 0 1
footprint=SOT26
T -1405 -1750 8 10 0 1 0 0 1
device=SN74LVC1T45