v 20061020 1 B 300 600 700 7400 3 0 0 0 0 0 0 -1 -1 -1 -1 -1 T 300 550 5 10 1 1 0 2 1 refdes=U? T 300 350 5 10 1 1 0 2 1 device=XC9536 T 200 550 5 10 0 0 0 8 1 copyright=2007 Ben Jackson T 200 350 5 10 0 0 0 8 1 author=Ben Jackson T 200 150 5 10 0 0 0 8 1 uselicense=unlimited T 200 -50 5 10 0 0 0 8 1 distlicense=GPL T 200 -250 5 10 0 0 0 8 1 description=Xilinx XC9536 T 200 -450 5 10 0 0 0 8 1 footprint=PLCC 44 P 1000 7800 1300 7800 1 0 1 { T 950 7800 5 8 1 1 0 7 1 pinlabel=IO T 1050 7825 5 8 1 1 0 0 1 pinnumber=1 T 1050 7825 5 8 0 1 0 0 1 pinseq=9 } P 1000 7600 1300 7600 1 0 1 { T 950 7600 5 8 1 1 0 7 1 pinlabel=IO T 1050 7625 5 8 1 1 0 0 1 pinnumber=2 T 1050 7625 5 8 0 1 0 0 1 pinseq=10 } P 1000 7400 1300 7400 1 0 1 { T 950 7400 5 8 1 1 0 7 1 pinlabel=IO T 1050 7425 5 8 1 1 0 0 1 pinnumber=3 T 1050 7425 5 8 0 1 0 0 1 pinseq=11 } P 1000 7200 1300 7200 1 0 1 { T 950 7200 5 8 1 1 0 7 1 pinlabel=IO T 1050 7225 5 8 1 1 0 0 1 pinnumber=4 T 1050 7225 5 8 0 1 0 0 1 pinseq=12 } P 1000 7000 1300 7000 1 0 1 { T 950 7000 5 8 1 1 0 7 1 pinlabel=GCK1/IO T 1050 7025 5 8 1 1 0 0 1 pinnumber=5 T 1050 7025 5 8 0 1 0 0 1 pinseq=13 } P 1000 6800 1300 6800 1 0 1 { T 950 6800 5 8 1 1 0 7 1 pinlabel=GCK2/IO T 1050 6825 5 8 1 1 0 0 1 pinnumber=6 T 1050 6825 5 8 0 1 0 0 1 pinseq=14 } P 1000 6600 1300 6600 1 0 1 { T 950 6600 5 8 1 1 0 7 1 pinlabel=GCK3/IO T 1050 6625 5 8 1 1 0 0 1 pinnumber=7 T 1050 6625 5 8 0 1 0 0 1 pinseq=15 } P 1000 6400 1300 6400 1 0 1 { T 950 6400 5 8 1 1 0 7 1 pinlabel=IO T 1050 6425 5 8 1 1 0 0 1 pinnumber=8 T 1050 6425 5 8 0 1 0 0 1 pinseq=16 } P 1000 6200 1300 6200 1 0 1 { T 950 6200 5 8 1 1 0 7 1 pinlabel=IO T 1050 6225 5 8 1 1 0 0 1 pinnumber=9 T 1050 6225 5 8 0 1 0 0 1 pinseq=17 } P 1000 6000 1300 6000 1 0 1 { T 950 6000 5 8 1 1 0 7 1 pinlabel=IO T 1050 6025 5 8 1 1 0 0 1 pinnumber=11 T 1050 6025 5 8 0 1 0 0 1 pinseq=18 } P 1000 5800 1300 5800 1 0 1 { T 950 5800 5 8 1 1 0 7 1 pinlabel=IO T 1050 5825 5 8 1 1 0 0 1 pinnumber=12 T 1050 5825 5 8 0 1 0 0 1 pinseq=19 } P 1000 5600 1300 5600 1 0 1 { T 950 5600 5 8 1 1 0 7 1 pinlabel=IO T 1050 5625 5 8 1 1 0 0 1 pinnumber=13 T 1050 5625 5 8 0 1 0 0 1 pinseq=20 } P 1000 5400 1300 5400 1 0 1 { T 950 5400 5 8 1 1 0 7 1 pinlabel=IO T 1050 5425 5 8 1 1 0 0 1 pinnumber=14 T 1050 5425 5 8 0 1 0 0 1 pinseq=21 } P 1000 5200 1300 5200 1 0 1 { T 950 5200 5 8 1 1 0 7 1 pinlabel=IO T 1050 5225 5 8 1 1 0 0 1 pinnumber=18 T 1050 5225 5 8 0 1 0 0 1 pinseq=22 } P 1000 5000 1300 5000 1 0 1 { T 950 5000 5 8 1 1 0 7 1 pinlabel=IO T 1050 5025 5 8 1 1 0 0 1 pinnumber=19 T 1050 5025 5 8 0 1 0 0 1 pinseq=23 } P 1000 4800 1300 4800 1 0 1 { T 950 4800 5 8 1 1 0 7 1 pinlabel=IO T 1050 4825 5 8 1 1 0 0 1 pinnumber=20 T 1050 4825 5 8 0 1 0 0 1 pinseq=24 } P 1000 4600 1300 4600 1 0 1 { T 950 4600 5 8 1 1 0 7 1 pinlabel=IO T 1050 4625 5 8 1 1 0 0 1 pinnumber=22 T 1050 4625 5 8 0 1 0 0 1 pinseq=25 } P 1000 4400 1300 4400 1 0 1 { T 950 4400 5 8 1 1 0 7 1 pinlabel=IO T 1050 4425 5 8 1 1 0 0 1 pinnumber=24 T 1050 4425 5 8 0 1 0 0 1 pinseq=26 } P 1000 4200 1300 4200 1 0 1 { T 950 4200 5 8 1 1 0 7 1 pinlabel=IO T 1050 4225 5 8 1 1 0 0 1 pinnumber=25 T 1050 4225 5 8 0 1 0 0 1 pinseq=27 } P 1000 4000 1300 4000 1 0 1 { T 950 4000 5 8 1 1 0 7 1 pinlabel=IO T 1050 4025 5 8 1 1 0 0 1 pinnumber=26 T 1050 4025 5 8 0 1 0 0 1 pinseq=28 } P 1000 3800 1300 3800 1 0 1 { T 950 3800 5 8 1 1 0 7 1 pinlabel=IO T 1050 3825 5 8 1 1 0 0 1 pinnumber=27 T 1050 3825 5 8 0 1 0 0 1 pinseq=29 } P 1000 3600 1300 3600 1 0 1 { T 950 3600 5 8 1 1 0 7 1 pinlabel=IO T 1050 3625 5 8 1 1 0 0 1 pinnumber=28 T 1050 3625 5 8 0 1 0 0 1 pinseq=30 } P 1000 3400 1300 3400 1 0 1 { T 950 3400 5 8 1 1 0 7 1 pinlabel=IO T 1050 3425 5 8 1 1 0 0 1 pinnumber=29 T 1050 3425 5 8 0 1 0 0 1 pinseq=31 } P 1000 3200 1300 3200 1 0 1 { T 950 3200 5 8 1 1 0 7 1 pinlabel=IO T 1050 3225 5 8 1 1 0 0 1 pinnumber=33 T 1050 3225 5 8 0 1 0 0 1 pinseq=32 } P 1000 3000 1300 3000 1 0 1 { T 950 3000 5 8 1 1 0 7 1 pinlabel=IO T 1050 3025 5 8 1 1 0 0 1 pinnumber=34 T 1050 3025 5 8 0 1 0 0 1 pinseq=33 } P 1000 2800 1300 2800 1 0 1 { T 950 2800 5 8 1 1 0 7 1 pinlabel=IO T 1050 2825 5 8 1 1 0 0 1 pinnumber=35 T 1050 2825 5 8 0 1 0 0 1 pinseq=34 } P 1000 2600 1300 2600 1 0 1 { T 950 2600 5 8 1 1 0 7 1 pinlabel=IO T 1050 2625 5 8 1 1 0 0 1 pinnumber=36 T 1050 2625 5 8 0 1 0 0 1 pinseq=35 } P 1000 2400 1300 2400 1 0 1 { T 950 2400 5 8 1 1 0 7 1 pinlabel=IO T 1050 2425 5 8 1 1 0 0 1 pinnumber=37 T 1050 2425 5 8 0 1 0 0 1 pinseq=36 } P 1000 2200 1300 2200 1 0 1 { T 950 2200 5 8 1 1 0 7 1 pinlabel=IO T 1050 2225 5 8 1 1 0 0 1 pinnumber=38 T 1050 2225 5 8 0 1 0 0 1 pinseq=37 } P 1000 2000 1300 2000 1 0 1 { T 950 2000 5 8 1 1 0 7 1 pinlabel=GSR/IO T 1050 2025 5 8 1 1 0 0 1 pinnumber=39 T 1050 2025 5 8 0 1 0 0 1 pinseq=38 } P 1000 1800 1300 1800 1 0 1 { T 950 1800 5 8 1 1 0 7 1 pinlabel=GTS2/IO T 1050 1825 5 8 1 1 0 0 1 pinnumber=40 T 1050 1825 5 8 0 1 0 0 1 pinseq=39 } P 1000 1600 1300 1600 1 0 1 { T 950 1600 5 8 1 1 0 7 1 pinlabel=GTS1/IO T 1050 1625 5 8 1 1 0 0 1 pinnumber=42 T 1050 1625 5 8 0 1 0 0 1 pinseq=40 } P 1000 1400 1300 1400 1 0 1 { T 950 1400 5 8 1 1 0 7 1 pinlabel=IO T 1050 1425 5 8 1 1 0 0 1 pinnumber=43 T 1050 1425 5 8 0 1 0 0 1 pinseq=41 } P 1000 1200 1300 1200 1 0 1 { T 950 1200 5 8 1 1 0 7 1 pinlabel=IO T 1050 1225 5 8 1 1 0 0 1 pinnumber=44 T 1050 1225 5 8 0 1 0 0 1 pinseq=42 } P 1000 800 1300 800 1 0 1 { T 950 800 5 8 1 1 0 7 1 pinlabel=VCCIO T 1050 825 5 8 1 1 0 0 1 pinnumber=32 T 1050 825 5 8 0 1 0 0 1 pinseq=43 }