v 20130925 2
P 100 5400 400 5400 1 0 0
{
T 300 5450 5 8 1 1 0 6 1
pinnumber=1
T 300 5350 5 8 0 1 0 8 1
pinseq=1
T 450 5400 9 8 1 1 0 0 1
pinlabel=P2[5] TRACEDATA[1], GPIO
T 450 5400 5 8 0 1 0 2 1
pintype=io
}
P 100 5200 400 5200 1 0 0
{
T 300 5250 5 8 1 1 0 6 1
pinnumber=2
T 300 5150 5 8 0 1 0 8 1
pinseq=2
T 450 5200 9 8 1 1 0 0 1
pinlabel=P2[6] TRACEDATA[2], GPIO
T 450 5200 5 8 0 1 0 2 1
pintype=io
}
P 100 5000 400 5000 1 0 0
{
T 300 5050 5 8 1 1 0 6 1
pinnumber=3
T 300 4950 5 8 0 1 0 8 1
pinseq=3
T 450 5000 9 8 1 1 0 0 1
pinlabel=P2[7] TRACEDATA[3], GPIO
T 450 5000 5 8 0 1 0 2 1
pintype=io
}
P 100 4800 400 4800 1 0 0
{
T 300 4850 5 8 1 1 0 6 1
pinnumber=4
T 300 4750 5 8 0 1 0 8 1
pinseq=4
T 450 4800 9 8 1 1 0 0 1
pinlabel=P12[4] I2C0: SCL, SIO
T 450 4800 5 8 0 1 0 2 1
pintype=io
}
P 100 4600 400 4600 1 0 0
{
T 300 4650 5 8 1 1 0 6 1
pinnumber=5
T 300 4550 5 8 0 1 0 8 1
pinseq=5
T 450 4600 9 8 1 1 0 0 1
pinlabel=P12[5] I2C0: SDA, SIO
T 450 4600 5 8 0 1 0 2 1
pintype=io
}
P 100 4400 400 4400 1 0 0
{
T 300 4450 5 8 1 1 0 6 1
pinnumber=6
T 300 4350 5 8 0 1 0 8 1
pinseq=6
T 450 4400 9 8 1 1 0 0 1
pinlabel=P6[4] GPIO
T 450 4400 5 8 0 1 0 2 1
pintype=io
}
P 100 4200 400 4200 1 0 0
{
T 300 4250 5 8 1 1 0 6 1
pinnumber=7
T 300 4150 5 8 0 1 0 8 1
pinseq=7
T 450 4200 9 8 1 1 0 0 1
pinlabel=P6[5] GPIO
T 450 4200 5 8 0 1 0 2 1
pintype=io
}
P 100 4000 400 4000 1 0 0
{
T 300 4050 5 8 1 1 0 6 1
pinnumber=8
T 300 3950 5 8 0 1 0 8 1
pinseq=8
T 450 4000 9 8 1 1 0 0 1
pinlabel=P6[6] GPIO
T 450 4000 5 8 0 1 0 2 1
pintype=io
}
P 100 3800 400 3800 1 0 0
{
T 300 3850 5 8 1 1 0 6 1
pinnumber=9
T 300 3750 5 8 0 1 0 8 1
pinseq=9
T 450 3800 9 8 1 1 0 0 1
pinlabel=P6[7] GPIO
T 450 3800 5 8 0 1 0 2 1
pintype=io
}
P 100 3600 400 3600 1 0 0
{
T 300 3650 5 8 1 1 0 6 1
pinnumber=10
T 300 3550 5 8 0 1 0 8 1
pinseq=10
T 450 3600 9 8 1 1 0 0 1
pinlabel=Vssb
T 450 3600 5 8 0 1 0 2 1
pintype=io
}
P 100 3400 400 3400 1 0 0
{
T 300 3450 5 8 1 1 0 6 1
pinnumber=11
T 300 3350 5 8 0 1 0 8 1
pinseq=11
T 450 3400 9 8 1 1 0 0 1
pinlabel=Ind
T 450 3400 5 8 0 1 0 2 1
pintype=io
}
P 100 3200 400 3200 1 0 0
{
T 300 3250 5 8 1 1 0 6 1
pinnumber=12
T 300 3150 5 8 0 1 0 8 1
pinseq=12
T 450 3200 9 8 1 1 0 0 1
pinlabel=Vboost
T 450 3200 5 8 0 1 0 2 1
pintype=io
}
P 100 3000 400 3000 1 0 0
{
T 300 3050 5 8 1 1 0 6 1
pinnumber=13
T 300 2950 5 8 0 1 0 8 1
pinseq=13
T 450 3000 9 8 1 1 0 0 1
pinlabel=Vbat
T 450 3000 5 8 0 1 0 2 1
pintype=io
}
P 100 2800 400 2800 1 0 0
{
T 300 2850 5 8 1 1 0 6 1
pinnumber=14
T 300 2750 5 8 0 1 0 8 1
pinseq=14
T 450 2800 9 8 1 1 0 0 1
pinlabel=Vssd
T 450 2800 5 8 0 1 0 2 1
pintype=io
}
P 100 2600 400 2600 1 0 0
{
T 300 2650 5 8 1 1 0 6 1
pinnumber=15
T 300 2550 5 8 0 1 0 8 1
pinseq=15
T 450 2600 9 8 1 1 0 0 1
pinlabel=\_XRES\_
T 450 2600 5 8 0 1 0 2 1
pintype=io
}
P 100 2400 400 2400 1 0 0
{
T 300 2450 5 8 1 1 0 6 1
pinnumber=16
T 300 2350 5 8 0 1 0 8 1
pinseq=16
T 450 2400 9 8 1 1 0 0 1
pinlabel=P5[0] GPIO
T 450 2400 5 8 0 1 0 2 1
pintype=io
}
P 100 2200 400 2200 1 0 0
{
T 300 2250 5 8 1 1 0 6 1
pinnumber=17
T 300 2150 5 8 0 1 0 8 1
pinseq=17
T 450 2200 9 8 1 1 0 0 1
pinlabel=P5[1] GPIO
T 450 2200 5 8 0 1 0 2 1
pintype=io
}
P 100 2000 400 2000 1 0 0
{
T 300 2050 5 8 1 1 0 6 1
pinnumber=18
T 300 1950 5 8 0 1 0 8 1
pinseq=18
T 450 2000 9 8 1 1 0 0 1
pinlabel=P5[2] GPIO
T 450 2000 5 8 0 1 0 2 1
pintype=io
}
P 100 1800 400 1800 1 0 0
{
T 300 1850 5 8 1 1 0 6 1
pinnumber=19
T 300 1750 5 8 0 1 0 8 1
pinseq=19
T 450 1800 9 8 1 1 0 0 1
pinlabel=P5[3] GPIO
T 450 1800 5 8 0 1 0 2 1
pintype=io
}
P 100 1600 400 1600 1 0 0
{
T 300 1650 5 8 1 1 0 6 1
pinnumber=20
T 300 1550 5 8 0 1 0 8 1
pinseq=20
T 450 1600 9 8 1 1 0 0 1
pinlabel=P1[0] TMS, SWDIO, GPIO
T 450 1600 5 8 0 1 0 2 1
pintype=io
}
P 100 1400 400 1400 1 0 0
{
T 300 1450 5 8 1 1 0 6 1
pinnumber=21
T 300 1350 5 8 0 1 0 8 1
pinseq=21
T 450 1400 9 8 1 1 0 0 1
pinlabel=P1[1] TCK, SWDCK, GPIO
T 450 1400 5 8 0 1 0 2 1
pintype=io
}
P 100 1200 400 1200 1 0 0
{
T 300 1250 5 8 1 1 0 6 1
pinnumber=22
T 300 1150 5 8 0 1 0 8 1
pinseq=22
T 450 1200 9 8 1 1 0 0 1
pinlabel=P1[2] conf_\XRES, GPIO
T 450 1200 5 8 0 1 0 2 1
pintype=io
}
P 100 1000 400 1000 1 0 0
{
T 300 1050 5 8 1 1 0 6 1
pinnumber=23
T 300 950 5 8 0 1 0 8 1
pinseq=23
T 450 1000 9 8 1 1 0 0 1
pinlabel=P1[3] TDO, SWV, GPIO
T 450 1000 5 8 0 1 0 2 1
pintype=io
}
P 100 800 400 800 1 0 0
{
T 300 850 5 8 1 1 0 6 1
pinnumber=24
T 300 750 5 8 0 1 0 8 1
pinseq=24
T 450 800 9 8 1 1 0 0 1
pinlabel=P1[4] TDI, GPIO
T 450 800 5 8 0 1 0 2 1
pintype=io
}
P 100 600 400 600 1 0 0
{
T 300 650 5 8 1 1 0 6 1
pinnumber=25
T 300 550 5 8 0 1 0 8 1
pinseq=25
T 450 600 9 8 1 1 0 0 1
pinlabel=P1[5] nTRST, GPIO
T 450 600 5 8 0 1 0 2 1
pintype=io
}
P 2500 100 2500 400 1 0 0
{
T 2450 300 5 8 1 1 90 6 1
pinnumber=26
T 2550 300 5 8 0 1 90 8 1
pinseq=26
T 2500 450 9 8 1 1 90 0 1
pinlabel=Vddio1
T 2500 450 5 8 0 1 90 2 1
pintype=io
}
P 2700 100 2700 400 1 0 0
{
T 2650 300 5 8 1 1 90 6 1
pinnumber=27
T 2750 300 5 8 0 1 90 8 1
pinseq=27
T 2700 450 9 8 1 1 90 0 1
pinlabel=P1[6] GPIO
T 2700 450 5 8 0 1 90 2 1
pintype=io
}
P 2900 100 2900 400 1 0 0
{
T 2850 300 5 8 1 1 90 6 1
pinnumber=28
T 2950 300 5 8 0 1 90 8 1
pinseq=28
T 2900 450 9 8 1 1 90 0 1
pinlabel=P1[7] GPIO
T 2900 450 5 8 0 1 90 2 1
pintype=io
}
P 3100 100 3100 400 1 0 0
{
T 3050 300 5 8 1 1 90 6 1
pinnumber=29
T 3150 300 5 8 0 1 90 8 1
pinseq=29
T 3100 450 9 8 1 1 90 0 1
pinlabel=P12[6] SIO
T 3100 450 5 8 0 1 90 2 1
pintype=io
}
P 3300 100 3300 400 1 0 0
{
T 3250 300 5 8 1 1 90 6 1
pinnumber=30
T 3350 300 5 8 0 1 90 8 1
pinseq=30
T 3300 450 9 8 1 1 90 0 1
pinlabel=P12[7] SIO
T 3300 450 5 8 0 1 90 2 1
pintype=io
}
P 3500 100 3500 400 1 0 0
{
T 3450 300 5 8 1 1 90 6 1
pinnumber=31
T 3550 300 5 8 0 1 90 8 1
pinseq=31
T 3500 450 9 8 1 1 90 0 1
pinlabel=P5[4] GPIO
T 3500 450 5 8 0 1 90 2 1
pintype=io
}
P 3700 100 3700 400 1 0 0
{
T 3650 300 5 8 1 1 90 6 1
pinnumber=32
T 3750 300 5 8 0 1 90 8 1
pinseq=32
T 3700 450 9 8 1 1 90 0 1
pinlabel=P5[5] GPIO
T 3700 450 5 8 0 1 90 2 1
pintype=io
}
P 3900 100 3900 400 1 0 0
{
T 3850 300 5 8 1 1 90 6 1
pinnumber=33
T 3950 300 5 8 0 1 90 8 1
pinseq=33
T 3900 450 9 8 1 1 90 0 1
pinlabel=P5[6] GPIO
T 3900 450 5 8 0 1 90 2 1
pintype=io
}
P 4100 100 4100 400 1 0 0
{
T 4050 300 5 8 1 1 90 6 1
pinnumber=34
T 4150 300 5 8 0 1 90 8 1
pinseq=34
T 4100 450 9 8 1 1 90 0 1
pinlabel=P5[7] GPIO
T 4100 450 5 8 0 1 90 2 1
pintype=io
}
P 4300 100 4300 400 1 0 0
{
T 4250 300 5 8 1 1 90 6 1
pinnumber=35
T 4350 300 5 8 0 1 90 8 1
pinseq=35
T 4300 450 9 8 1 1 90 0 1
pinlabel=P15[6] USBIO, D+, SWDIO
T 4300 450 5 8 0 1 90 2 1
pintype=io
}
P 4500 100 4500 400 1 0 0
{
T 4450 300 5 8 1 1 90 6 1
pinnumber=36
T 4550 300 5 8 0 1 90 8 1
pinseq=36
T 4500 450 9 8 1 1 90 0 1
pinlabel=P15[7] USBIO, D-, SWDCK
T 4500 450 5 8 0 1 90 2 1
pintype=io
}
P 4700 100 4700 400 1 0 0
{
T 4650 300 5 8 1 1 90 6 1
pinnumber=37
T 4750 300 5 8 0 1 90 8 1
pinseq=37
T 4700 450 9 8 1 1 90 0 1
pinlabel=Vddd
T 4700 450 5 8 0 1 90 2 1
pintype=io
}
P 4900 100 4900 400 1 0 0
{
T 4850 300 5 8 1 1 90 6 1
pinnumber=38
T 4950 300 5 8 0 1 90 8 1
pinseq=38
T 4900 450 9 8 1 1 90 0 1
pinlabel=Vssd
T 4900 450 5 8 0 1 90 2 1
pintype=io
}
P 5100 100 5100 400 1 0 0
{
T 5050 300 5 8 1 1 90 6 1
pinnumber=39
T 5150 300 5 8 0 1 90 8 1
pinseq=39
T 5100 450 9 8 1 1 90 0 1
pinlabel=Vccd
T 5100 450 5 8 0 1 90 2 1
pintype=io
}
P 5300 100 5300 400 1 0 0
{
T 5250 300 5 8 1 1 90 6 1
pinnumber=40
T 5350 300 5 8 0 1 90 8 1
pinseq=40
T 5300 450 9 8 1 1 90 0 1
pinlabel=NC
T 5300 450 5 8 0 1 90 2 1
pintype=io
}
P 5500 100 5500 400 1 0 0
{
T 5450 300 5 8 1 1 90 6 1
pinnumber=41
T 5550 300 5 8 0 1 90 8 1
pinseq=41
T 5500 450 9 8 1 1 90 0 1
pinlabel=NC
T 5500 450 5 8 0 1 90 2 1
pintype=io
}
P 5700 100 5700 400 1 0 0
{
T 5650 300 5 8 1 1 90 6 1
pinnumber=42
T 5750 300 5 8 0 1 90 8 1
pinseq=42
T 5700 450 9 8 1 1 90 0 1
pinlabel=P15[0] MHz XTAL: Xo, GPIO
T 5700 450 5 8 0 1 90 2 1
pintype=io
}
P 5900 100 5900 400 1 0 0
{
T 5850 300 5 8 1 1 90 6 1
pinnumber=43
T 5950 300 5 8 0 1 90 8 1
pinseq=43
T 5900 450 9 8 1 1 90 0 1
pinlabel=P15[1] MHz XTAL: Xi, GPIO
T 5900 450 5 8 0 1 90 2 1
pintype=io
}
P 6100 100 6100 400 1 0 0
{
T 6050 300 5 8 1 1 90 6 1
pinnumber=44
T 6150 300 5 8 0 1 90 8 1
pinseq=44
T 6100 450 9 8 1 1 90 0 1
pinlabel=P3[0] IDAC1, GPIO
T 6100 450 5 8 0 1 90 2 1
pintype=io
}
P 6300 100 6300 400 1 0 0
{
T 6250 300 5 8 1 1 90 6 1
pinnumber=45
T 6350 300 5 8 0 1 90 8 1
pinseq=45
T 6300 450 9 8 1 1 90 0 1
pinlabel=P3[1] IDAC3, GPIO
T 6300 450 5 8 0 1 90 2 1
pintype=io
}
P 6500 100 6500 400 1 0 0
{
T 6450 300 5 8 1 1 90 6 1
pinnumber=46
T 6550 300 5 8 0 1 90 8 1
pinseq=46
T 6500 450 9 8 1 1 90 0 1
pinlabel=P3[2] OpAmp3-/Extref1, GPIO
T 6500 450 5 8 0 1 90 2 1
pintype=io
}
P 6700 100 6700 400 1 0 0
{
T 6650 300 5 8 1 1 90 6 1
pinnumber=47
T 6750 300 5 8 0 1 90 8 1
pinseq=47
T 6700 450 9 8 1 1 90 0 1
pinlabel=P3[3] OpAmp3+, GPIO
T 6700 450 5 8 0 1 90 2 1
pintype=io
}
P 6900 100 6900 400 1 0 0
{
T 6850 300 5 8 1 1 90 6 1
pinnumber=48
T 6950 300 5 8 0 1 90 8 1
pinseq=48
T 6900 450 9 8 1 1 90 0 1
pinlabel=P3[4] OpAmp1-, GPIO
T 6900 450 5 8 0 1 90 2 1
pintype=io
}
P 7100 100 7100 400 1 0 0
{
T 7050 300 5 8 1 1 90 6 1
pinnumber=49
T 7150 300 5 8 0 1 90 8 1
pinseq=49
T 7100 450 9 8 1 1 90 0 1
pinlabel=P3[5] OpAmp1+, GPIO
T 7100 450 5 8 0 1 90 2 1
pintype=io
}
P 7300 100 7300 400 1 0 0
{
T 7250 300 5 8 1 1 90 6 1
pinnumber=50
T 7350 300 5 8 0 1 90 8 1
pinseq=50
T 7300 450 9 8 1 1 90 0 1
pinlabel=Vddio3
T 7300 450 5 8 0 1 90 2 1
pintype=io
}
P 9700 5400 9400 5400 1 0 0
{
T 9500 5450 5 8 1 1 0 0 1
pinnumber=75
T 9500 5350 5 8 0 1 0 2 1
pinseq=51
T 9350 5400 9 8 1 1 0 6 1
pinlabel=Vddio0
T 9350 5400 5 8 0 1 0 8 1
pintype=io
}
P 9700 5200 9400 5200 1 0 0
{
T 9500 5250 5 8 1 1 0 0 1
pinnumber=74
T 9500 5150 5 8 0 1 0 2 1
pinseq=52
T 9350 5200 9 8 1 1 0 6 1
pinlabel=OpAmp0-/Extref0 GPIO, P0[3]
T 9350 5200 5 8 0 1 0 8 1
pintype=io
}
P 9700 5000 9400 5000 1 0 0
{
T 9500 5050 5 8 1 1 0 0 1
pinnumber=73
T 9500 4950 5 8 0 1 0 2 1
pinseq=53
T 9350 5000 9 8 1 1 0 6 1
pinlabel=OpAmp0+ GPIO, P0[2]
T 9350 5000 5 8 0 1 0 8 1
pintype=io
}
P 9700 4800 9400 4800 1 0 0
{
T 9500 4850 5 8 1 1 0 0 1
pinnumber=72
T 9500 4750 5 8 0 1 0 2 1
pinseq=54
T 9350 4800 9 8 1 1 0 6 1
pinlabel=OpAmp0out GPIO, P0[1]
T 9350 4800 5 8 0 1 0 8 1
pintype=io
}
P 9700 4600 9400 4600 1 0 0
{
T 9500 4650 5 8 1 1 0 0 1
pinnumber=71
T 9500 4550 5 8 0 1 0 2 1
pinseq=55
T 9350 4600 9 8 1 1 0 6 1
pinlabel=OpAmp2out GPIO, P0[0]
T 9350 4600 5 8 0 1 0 8 1
pintype=io
}
P 9700 4400 9400 4400 1 0 0
{
T 9500 4450 5 8 1 1 0 0 1
pinnumber=70
T 9500 4350 5 8 0 1 0 2 1
pinseq=56
T 9350 4400 9 8 1 1 0 6 1
pinlabel=GPIO P4[1]
T 9350 4400 5 8 0 1 0 8 1
pintype=io
}
P 9700 4200 9400 4200 1 0 0
{
T 9500 4250 5 8 1 1 0 0 1
pinnumber=69
T 9500 4150 5 8 0 1 0 2 1
pinseq=57
T 9350 4200 9 8 1 1 0 6 1
pinlabel=GPIO P4[0]
T 9350 4200 5 8 0 1 0 8 1
pintype=io
}
P 9700 4000 9400 4000 1 0 0
{
T 9500 4050 5 8 1 1 0 0 1
pinnumber=68
T 9500 3950 5 8 0 1 0 2 1
pinseq=58
T 9350 4000 9 8 1 1 0 6 1
pinlabel=SIO P12[3]
T 9350 4000 5 8 0 1 0 8 1
pintype=io
}
P 9700 3800 9400 3800 1 0 0
{
T 9500 3850 5 8 1 1 0 0 1
pinnumber=67
T 9500 3750 5 8 0 1 0 2 1
pinseq=59
T 9350 3800 9 8 1 1 0 6 1
pinlabel=SIO P12[2]
T 9350 3800 5 8 0 1 0 8 1
pintype=io
}
P 9700 3600 9400 3600 1 0 0
{
T 9500 3650 5 8 1 1 0 0 1
pinnumber=66
T 9500 3550 5 8 0 1 0 2 1
pinseq=60
T 9350 3600 9 8 1 1 0 6 1
pinlabel=Vssd
T 9350 3600 5 8 0 1 0 8 1
pintype=io
}
P 9700 3400 9400 3400 1 0 0
{
T 9500 3450 5 8 1 1 0 0 1
pinnumber=65
T 9500 3350 5 8 0 1 0 2 1
pinseq=61
T 9350 3400 9 8 1 1 0 6 1
pinlabel=Vdda
T 9350 3400 5 8 0 1 0 8 1
pintype=io
}
P 9700 3200 9400 3200 1 0 0
{
T 9500 3250 5 8 1 1 0 0 1
pinnumber=64
T 9500 3150 5 8 0 1 0 2 1
pinseq=62
T 9350 3200 9 8 1 1 0 6 1
pinlabel=Vssa
T 9350 3200 5 8 0 1 0 8 1
pintype=io
}
P 9700 3000 9400 3000 1 0 0
{
T 9500 3050 5 8 1 1 0 0 1
pinnumber=63
T 9500 2950 5 8 0 1 0 2 1
pinseq=63
T 9350 3000 9 8 1 1 0 6 1
pinlabel=Vcca
T 9350 3000 5 8 0 1 0 8 1
pintype=io
}
P 9700 2800 9400 2800 1 0 0
{
T 9500 2850 5 8 1 1 0 0 1
pinnumber=62
T 9500 2750 5 8 0 1 0 2 1
pinseq=64
T 9350 2800 9 8 1 1 0 6 1
pinlabel=NC
T 9350 2800 5 8 0 1 0 8 1
pintype=io
}
P 9700 2600 9400 2600 1 0 0
{
T 9500 2650 5 8 1 1 0 0 1
pinnumber=61
T 9500 2550 5 8 0 1 0 2 1
pinseq=65
T 9350 2600 9 8 1 1 0 6 1
pinlabel=NC
T 9350 2600 5 8 0 1 0 8 1
pintype=io
}
P 9700 2400 9400 2400 1 0 0
{
T 9500 2450 5 8 1 1 0 0 1
pinnumber=60
T 9500 2350 5 8 0 1 0 2 1
pinseq=66
T 9350 2400 9 8 1 1 0 6 1
pinlabel=NC
T 9350 2400 5 8 0 1 0 8 1
pintype=io
}
P 9700 2200 9400 2200 1 0 0
{
T 9500 2250 5 8 1 1 0 0 1
pinnumber=59
T 9500 2150 5 8 0 1 0 2 1
pinseq=67
T 9350 2200 9 8 1 1 0 6 1
pinlabel=NC
T 9350 2200 5 8 0 1 0 8 1
pintype=io
}
P 9700 2000 9400 2000 1 0 0
{
T 9500 2050 5 8 1 1 0 0 1
pinnumber=58
T 9500 1950 5 8 0 1 0 2 1
pinseq=68
T 9350 2000 9 8 1 1 0 6 1
pinlabel=NC
T 9350 2000 5 8 0 1 0 8 1
pintype=io
}
P 9700 1800 9400 1800 1 0 0
{
T 9500 1850 5 8 1 1 0 0 1
pinnumber=57
T 9500 1750 5 8 0 1 0 2 1
pinseq=69
T 9350 1800 9 8 1 1 0 6 1
pinlabel=NC
T 9350 1800 5 8 0 1 0 8 1
pintype=io
}
P 9700 1600 9400 1600 1 0 0
{
T 9500 1650 5 8 1 1 0 0 1
pinnumber=56
T 9500 1550 5 8 0 1 0 2 1
pinseq=70
T 9350 1600 9 8 1 1 0 6 1
pinlabel=Xi XTAL: kHz GPIO, P15[3]
T 9350 1600 5 8 0 1 0 8 1
pintype=io
}
P 9700 1400 9400 1400 1 0 0
{
T 9500 1450 5 8 1 1 0 0 1
pinnumber=55
T 9500 1350 5 8 0 1 0 2 1
pinseq=71
T 9350 1400 9 8 1 1 0 6 1
pinlabel=Xo XTAL: kHz GPIO, P15[2]
T 9350 1400 5 8 0 1 0 8 1
pintype=io
}
P 9700 1200 9400 1200 1 0 0
{
T 9500 1250 5 8 1 1 0 0 1
pinnumber=54
T 9500 1150 5 8 0 1 0 2 1
pinseq=72
T 9350 1200 9 8 1 1 0 6 1
pinlabel=SDA I2C1: SIO, P12[1]
T 9350 1200 5 8 0 1 0 8 1
pintype=io
}
P 9700 1000 9400 1000 1 0 0
{
T 9500 1050 5 8 1 1 0 0 1
pinnumber=53
T 9500 950 5 8 0 1 0 2 1
pinseq=73
T 9350 1000 9 8 1 1 0 6 1
pinlabel=SCL I2C1: SIO, P12[0]
T 9350 1000 5 8 0 1 0 8 1
pintype=io
}
P 9700 800 9400 800 1 0 0
{
T 9500 850 5 8 1 1 0 0 1
pinnumber=52
T 9500 750 5 8 0 1 0 2 1
pinseq=74
T 9350 800 9 8 1 1 0 6 1
pinlabel=OpAmp3out GPIO, P3[7]
T 9350 800 5 8 0 1 0 8 1
pintype=io
}
P 9700 600 9400 600 1 0 0
{
T 9500 650 5 8 1 1 0 0 1
pinnumber=51
T 9500 550 5 8 0 1 0 2 1
pinseq=75
T 9350 600 9 8 1 1 0 6 1
pinlabel=OpAmp1out GPIO, P3[6]
T 9350 600 5 8 0 1 0 8 1
pintype=io
}
P 2500 5900 2500 5600 1 0 0
{
T 2450 5700 5 8 1 1 90 0 1
pinnumber=100
T 2550 5700 5 8 0 1 90 2 1
pinseq=76
T 2500 5550 9 8 1 1 90 6 1
pinlabel=Vddio2
T 2500 5550 5 8 0 1 90 8 1
pintype=io
}
P 2700 5900 2700 5600 1 0 0
{
T 2650 5700 5 8 1 1 90 0 1
pinnumber=99
T 2750 5700 5 8 0 1 90 2 1
pinseq=77
T 2700 5550 9 8 1 1 90 6 1
pinlabel=TRACEDATA[0] GPIO, P2[4]
T 2700 5550 5 8 0 1 90 8 1
pintype=io
}
P 2900 5900 2900 5600 1 0 0
{
T 2850 5700 5 8 1 1 90 0 1
pinnumber=98
T 2950 5700 5 8 0 1 90 2 1
pinseq=78
T 2900 5550 9 8 1 1 90 6 1
pinlabel=TRACECLK GPIO, P2[3]
T 2900 5550 5 8 0 1 90 8 1
pintype=io
}
P 3100 5900 3100 5600 1 0 0
{
T 3050 5700 5 8 1 1 90 0 1
pinnumber=97
T 3150 5700 5 8 0 1 90 2 1
pinseq=79
T 3100 5550 9 8 1 1 90 6 1
pinlabel=GPIO P2[2]
T 3100 5550 5 8 0 1 90 8 1
pintype=io
}
P 3300 5900 3300 5600 1 0 0
{
T 3250 5700 5 8 1 1 90 0 1
pinnumber=96
T 3350 5700 5 8 0 1 90 2 1
pinseq=80
T 3300 5550 9 8 1 1 90 6 1
pinlabel=GPIO P2[1]
T 3300 5550 5 8 0 1 90 8 1
pintype=io
}
P 3500 5900 3500 5600 1 0 0
{
T 3450 5700 5 8 1 1 90 0 1
pinnumber=95
T 3550 5700 5 8 0 1 90 2 1
pinseq=81
T 3500 5550 9 8 1 1 90 6 1
pinlabel=GPIO P2[0]
T 3500 5550 5 8 0 1 90 8 1
pintype=io
}
P 3700 5900 3700 5600 1 0 0
{
T 3650 5700 5 8 1 1 90 0 1
pinnumber=94
T 3750 5700 5 8 0 1 90 2 1
pinseq=82
T 3700 5550 9 8 1 1 90 6 1
pinlabel=GPIO P15[5]
T 3700 5550 5 8 0 1 90 8 1
pintype=io
}
P 3900 5900 3900 5600 1 0 0
{
T 3850 5700 5 8 1 1 90 0 1
pinnumber=93
T 3950 5700 5 8 0 1 90 2 1
pinseq=83
T 3900 5550 9 8 1 1 90 6 1
pinlabel=GPIO P15[4]
T 3900 5550 5 8 0 1 90 8 1
pintype=io
}
P 4100 5900 4100 5600 1 0 0
{
T 4050 5700 5 8 1 1 90 0 1
pinnumber=92
T 4150 5700 5 8 0 1 90 2 1
pinseq=84
T 4100 5550 9 8 1 1 90 6 1
pinlabel=GPIO P6[3]
T 4100 5550 5 8 0 1 90 8 1
pintype=io
}
P 4300 5900 4300 5600 1 0 0
{
T 4250 5700 5 8 1 1 90 0 1
pinnumber=91
T 4350 5700 5 8 0 1 90 2 1
pinseq=85
T 4300 5550 9 8 1 1 90 6 1
pinlabel=GPIO P6[2]
T 4300 5550 5 8 0 1 90 8 1
pintype=io
}
P 4500 5900 4500 5600 1 0 0
{
T 4450 5700 5 8 1 1 90 0 1
pinnumber=90
T 4550 5700 5 8 0 1 90 2 1
pinseq=86
T 4500 5550 9 8 1 1 90 6 1
pinlabel=GPIO P6[1]
T 4500 5550 5 8 0 1 90 8 1
pintype=io
}
P 4700 5900 4700 5600 1 0 0
{
T 4650 5700 5 8 1 1 90 0 1
pinnumber=89
T 4750 5700 5 8 0 1 90 2 1
pinseq=87
T 4700 5550 9 8 1 1 90 6 1
pinlabel=GPIO P6[0]
T 4700 5550 5 8 0 1 90 8 1
pintype=io
}
P 4900 5900 4900 5600 1 0 0
{
T 4850 5700 5 8 1 1 90 0 1
pinnumber=88
T 4950 5700 5 8 0 1 90 2 1
pinseq=88
T 4900 5550 9 8 1 1 90 6 1
pinlabel=Vddd
T 4900 5550 5 8 0 1 90 8 1
pintype=io
}
P 5100 5900 5100 5600 1 0 0
{
T 5050 5700 5 8 1 1 90 0 1
pinnumber=87
T 5150 5700 5 8 0 1 90 2 1
pinseq=89
T 5100 5550 9 8 1 1 90 6 1
pinlabel=Vssd
T 5100 5550 5 8 0 1 90 8 1
pintype=io
}
P 5300 5900 5300 5600 1 0 0
{
T 5250 5700 5 8 1 1 90 0 1
pinnumber=86
T 5350 5700 5 8 0 1 90 2 1
pinseq=90
T 5300 5550 9 8 1 1 90 6 1
pinlabel=Vccd
T 5300 5550 5 8 0 1 90 8 1
pintype=io
}
P 5500 5900 5500 5600 1 0 0
{
T 5450 5700 5 8 1 1 90 0 1
pinnumber=85
T 5550 5700 5 8 0 1 90 2 1
pinseq=91
T 5500 5550 9 8 1 1 90 6 1
pinlabel=GPIO P4[7]
T 5500 5550 5 8 0 1 90 8 1
pintype=io
}
P 5700 5900 5700 5600 1 0 0
{
T 5650 5700 5 8 1 1 90 0 1
pinnumber=84
T 5750 5700 5 8 0 1 90 2 1
pinseq=92
T 5700 5550 9 8 1 1 90 6 1
pinlabel=GPIO P4[6]
T 5700 5550 5 8 0 1 90 8 1
pintype=io
}
P 5900 5900 5900 5600 1 0 0
{
T 5850 5700 5 8 1 1 90 0 1
pinnumber=83
T 5950 5700 5 8 0 1 90 2 1
pinseq=93
T 5900 5550 9 8 1 1 90 6 1
pinlabel=GPIO P4[5]
T 5900 5550 5 8 0 1 90 8 1
pintype=io
}
P 6100 5900 6100 5600 1 0 0
{
T 6050 5700 5 8 1 1 90 0 1
pinnumber=82
T 6150 5700 5 8 0 1 90 2 1
pinseq=94
T 6100 5550 9 8 1 1 90 6 1
pinlabel=GPIO P4[4]
T 6100 5550 5 8 0 1 90 8 1
pintype=io
}
P 6300 5900 6300 5600 1 0 0
{
T 6250 5700 5 8 1 1 90 0 1
pinnumber=81
T 6350 5700 5 8 0 1 90 2 1
pinseq=95
T 6300 5550 9 8 1 1 90 6 1
pinlabel=GPIO P4[3]
T 6300 5550 5 8 0 1 90 8 1
pintype=io
}
P 6500 5900 6500 5600 1 0 0
{
T 6450 5700 5 8 1 1 90 0 1
pinnumber=80
T 6550 5700 5 8 0 1 90 2 1
pinseq=96
T 6500 5550 9 8 1 1 90 6 1
pinlabel=GPIO P4[2]
T 6500 5550 5 8 0 1 90 8 1
pintype=io
}
P 6700 5900 6700 5600 1 0 0
{
T 6650 5700 5 8 1 1 90 0 1
pinnumber=79
T 6750 5700 5 8 0 1 90 2 1
pinseq=97
T 6700 5550 9 8 1 1 90 6 1
pinlabel=IDAC2 GPIO, P0[7]
T 6700 5550 5 8 0 1 90 8 1
pintype=io
}
P 6900 5900 6900 5600 1 0 0
{
T 6850 5700 5 8 1 1 90 0 1
pinnumber=78
T 6950 5700 5 8 0 1 90 2 1
pinseq=98
T 6900 5550 9 8 1 1 90 6 1
pinlabel=IDAC0 GPIO, P0[6]
T 6900 5550 5 8 0 1 90 8 1
pintype=io
}
P 7100 5900 7100 5600 1 0 0
{
T 7050 5700 5 8 1 1 90 0 1
pinnumber=77
T 7150 5700 5 8 0 1 90 2 1
pinseq=99
T 7100 5550 9 8 1 1 90 6 1
pinlabel=OpAmp2- GPIO, P0[5]
T 7100 5550 5 8 0 1 90 8 1
pintype=io
}
P 7300 5900 7300 5600 1 0 0
{
T 7250 5700 5 8 1 1 90 0 1
pinnumber=76
T 7350 5700 5 8 0 1 90 2 1
pinseq=100
T 7300 5550 9 8 1 1 90 6 1
pinlabel=OpAmp2+ GPIO, P0[4]
T 7300 5550 5 8 0 1 90 8 1
pintype=io
}
B 400 400 9000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 9400 5700 8 10 1 1 0 6 1
refdes=U?
T 3900 2900 9 10 1 0 0 0 2
PsoC5 CY8C5588AXI 
           TQFP100
T 4700 3200 5 10 0 0 0 0 1
device=PsoC5 CY8C5588AXI
T 4700 3400 5 10 0 0 0 0 1
footprint=100TQFP-PSOC
T 4700 3600 5 10 0 0 0 0 1
author=Abhijit Kshirsagar- abhijit 86k at gm ail dot com
T 4700 3800 5 10 0 0 0 0 1
documentation=TBD
T 4700 4000 5 10 0 0 0 0 1
description=PsoC 5 100pin TQFP
T 4700 4200 5 10 0 0 0 0 1
numslots=0
T 4700 3000 8 10 0 0 0 0 1
dist-license=GPLv2
T 4700 2800 8 10 0 0 0 0 1
use-license=GPLv2